<p>Werner Zeh <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30128">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Mario Scheithauer: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">siemens/mc_apl4: Add GPIO configuration<br><br>Add GPIO configuration to match the hardware of mc_apl4.<br><br>Change-Id: Ia69603f42c57c1cc682550b8eeeab42fbac27563<br>Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com><br>Reviewed-on: https://review.coreboot.org/c/30128<br>Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com><br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>---<br>M src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc<br>A src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c<br>2 files changed, 392 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc</span><br><span>index fd45b94..0a124ce 100644</span><br><span>--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc</span><br><span>@@ -1 +1,4 @@</span><br><span> romstage-y += memory.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += gpio.c</span><br><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c</span><br><span>new file mode 100644</span><br><span>index 0000000..40b2c93</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c</span><br><span>@@ -0,0 +1,389 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2016 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017-2018 Siemens AG</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <commonlib/helpers.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variants.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing'</span><br><span style="color: hsl(120, 100%, 40%);">+ * table found in EDS vol 1, but some pins aren't grouped functionally in</span><br><span style="color: hsl(120, 100%, 40%);">+ * the table so those were moved for more logical grouping.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_config gpio_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Southwest Community */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCIE_WAKE[0:3]_N - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_205, UP_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_206, UP_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_207, UP_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_208, UP_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* EMMC interface. */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1), /* EMMC_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_157, UP_20K, DEEP, NF1), /* EMMC_D0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_158, UP_20K, DEEP, NF1), /* EMMC_D1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_159, UP_20K, DEEP, NF1), /* EMMC_D2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_160, UP_20K, DEEP, NF1), /* EMMC_D3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_161, UP_20K, DEEP, NF1), /* EMMC_D4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_162, UP_20K, DEEP, NF1), /* EMMC_D5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_163, UP_20K, DEEP, NF1), /* EMMC_D6 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_164, UP_20K, DEEP, NF1), /* EMMC_D7 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_165, UP_20K, DEEP, NF1), /* EMMC_CMD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1), /* EMMC_RCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SDIO - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_166, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_167, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_168, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_169, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_170, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_171, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SDCARD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1), /* SDCARD_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1), /* SDCARD_D0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1), /* SDCARD_D1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1), /* SDCARD_D2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1), /* SDCARD_D3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_177, UP_20K, DEEP, NF1), /* SDCARD_CD_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1), /* SDCARD_CMD */</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * SDCARD_CLK_FB - APL EDS Vol1 remarks:</span><br><span style="color: hsl(120, 100%, 40%);">+ * This is not a physical GPIO that can be used. This Signal is not Ball</span><br><span style="color: hsl(120, 100%, 40%);">+ * out on the SoC, only the buffer exists.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_186, UP_20K, DEEP, NF1), /* SDCARD_WP_1V8 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_TERM_GPO(GPIO_183, 1, UP_20K, DEEP), /* SD_PWR_EN_1V8 */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* West Community */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_124, DN_20K, DEEP), /* unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_125, DN_20K, DEEP), /* unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_126, DN_20K, DEEP), /* unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_127, DN_20K, DEEP), /* unused */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_128, NONE, DEEP, NF1), /* provided LPSS_I2C2_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_129, NONE, DEEP, NF1), /* provided LPSS_I2C2_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_130, DN_20K, DEEP), /* unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_131, DN_20K, DEEP), /* unused */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_132, NONE, DEEP, NF1), /* provided LPSS_I2C4_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_133, NONE, DEEP, NF1), /* provided LPSS_I2C4_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Hint for USB enable power: some GPIOs are open drain outputs,</span><br><span style="color: hsl(120, 100%, 40%);">+ * to drive high -> Bit GPIO_TX_DIS has to be set in combination with PU</span><br><span style="color: hsl(120, 100%, 40%);">+ * PAD_CFG_GPO macro does not work. Refer to APL EDS Vol 4.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_134, UP_20K, DEEP), /* enable USB0 power */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_135, UP_20K, DEEP), /* unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_136, UP_20K, DEEP), /* enable USB7 power */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_137, UP_20K, DEEP), /* enable USB6 power */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_138, UP_20K, DEEP), /* enable USB2 power */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_139, UP_20K, DEEP), /* enable USB1 power */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ISH_GPIO_[0:9] -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_146, DN_20K, DEEP), /* ISH_GPIO_0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_147, DN_20K, DEEP), /* ISH_GPIO_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_148, DN_20K, DEEP), /* ISH_GPIO_2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_149, DN_20K, DEEP), /* ISH_GPIO_3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_150, DN_20K, DEEP), /* ISH_GPIO_4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_151, DN_20K, DEEP), /* ISH_GPIO_5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_152, DN_20K, DEEP), /* ISH_GPIO_6 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_153, DN_20K, DEEP), /* ISH_GPIO_7 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_154, DN_20K, DEEP), /* ISH_GPIO_8 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_155, DN_20K, DEEP), /* ISH_GPIO_9 */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCIE_CLKREQ[0:3]_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_209, DN_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_210, DN_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_211, DN_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_212, DN_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* OSC_CLK_OUT_[0:4] - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(OSC_CLK_OUT_0, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(OSC_CLK_OUT_1, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(OSC_CLK_OUT_2, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(OSC_CLK_OUT_3, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(OSC_CLK_OUT_4, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PMU Signals */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(PMU_AC_PRESENT, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(PMU_SLP_S0_B, UP_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(PMU_SLP_S3_B, UP_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(PMU_SLP_S4_B, UP_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(PMU_SUSCLK, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(PMU_WAKE_B, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(SUS_STAT_B, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(SUSPWRDNACK, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Northwest Community */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DDI0 SDA and SCL - Display-Port X24 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_187, UP_20K, DEEP, NF1), /* HV_DDI0_DDC_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_188, UP_20K, DEEP, NF1), /* HV_DDI0_DDC_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DDI1 SDA and SCL - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_189, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_190, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* MIPI I2C - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_191, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_192, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Panel 0 control - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_193, DN_20K, DEEP), /* PNL0_VDDEN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_194, DN_20K, DEEP), /* PNL0_BKLTEN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_195, DN_20K, DEEP), /* PNL0_BKLTCTL */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Panel 1 control - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_196, DN_20K, DEEP), /* PNL1_VDDEN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_197, DN_20K, DEEP), /* PNL1_BKLTEN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_198, DN_20K, DEEP), /* PNL1_BKLTCTL */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DDI[0:1]_HPD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_199, UP_20K, DEEP), /* DDI1_HPD unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2), /* DDI0_HDP X24 */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* MDSI signals - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_201, DN_20K, DEEP), /* MDSI_A_TE */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_202, DN_20K, DEEP), /* MDSI_C_TE */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* USB overcurrent pins. */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_203, UP_20K, DEEP, NF1), /* USB_OC0_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_204, UP_20K, DEEP, NF1), /* USB_OC1_N */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PMC SPI */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(PMC_SPI_FS0, DN_20K, DEEP), /* unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF2), /* XHPD_EDP_APL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(PMC_SPI_FS2, DN_20K, DEEP), /* unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(PMC_SPI_RXD, DN_20K, DEEP), /* unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(PMC_SPI_TXD, DN_20K, DEEP), /* unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(PMC_SPI_CLK, DN_20K, DEEP), /* unused */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PMIC Signals unused signals related to an old PMIC interface. */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(PMIC_PWRGOOD, DN_20K, DEEP), /* PMIC_PWRGOOD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(PMIC_RESET_B, DN_20K, DEEP), /* PMIC_RESET_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_213, UP_20K, DEEP), /* PMIC_SDWN_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_214, DN_20K, DEEP), /* PMIC_BCUDISW2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_215, DN_20K, DEEP), /* PMIC_BCUDISCRIT */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1),/* THERMTRIP_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(PMIC_STDBY, DN_20K, DEEP), /* PMIC_STDBY */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1), /* PROCHOT_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(PMIC_I2C_SCL, DN_20K, DEEP), /* unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(PMIC_I2C_SDA, DN_20K, DEEP), /* unused */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* I2S1 - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_74, DN_20K, DEEP), /* I2S1_MCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_75, DN_20K, DEEP), /* I2S1_BCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_76, DN_20K, DEEP), /* I2S1_WS_SYNC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_77, DN_20K, DEEP), /* I2S1_SDI */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_78, DN_20K, DEEP), /* I2S1_SDO */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DMIC or I2S4 - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_79, DN_20K, DEEP), /* AVS_M_CLK_A1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_80, DN_20K, DEEP), /* AVS_M_CLK_B1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_81, DN_20K, DEEP), /* AVS_M_DATA_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_82, DN_20K, DEEP), /* AVS_M_CLK_AB2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_83, DN_20K, DEEP), /* AVS_M_DATA_2 */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* I2S2 - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPIO_84, 0, DEEP), /* AVS_I2S2_MCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_85, DN_20K, DEEP), /* AVS_I2S2_BCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_86, DN_20K, DEEP), /* AVS_I2S2_WS_SYNC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_87, DN_20K, DEEP), /* AVS_I2S2_SDI */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_88, DN_20K, DEEP), /* AVS_I2S2_SDO */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* I2S3 - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_89, DN_20K, DEEP), /* AVS_I2S3_BCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_90, DN_20K, DEEP), /* AVS_I2S3_WS_SYNC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_91, DN_20K, DEEP), /* AVS_I2S3_SDI */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_92, DN_20K, DEEP), /* AVS_I2S3_SDO */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Fast SPI for mainboard Flash and TPM on mainboard. */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_97, NATIVE, DEEP, NF1), /* FST_SPI_CS0_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_98, DN_20K, DEEP), /* FST_SPI_CS1_B - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_99, NATIVE, DEEP, NF1), /* FST_SPI_MOSI_IO0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_100, NATIVE, DEEP, NF1),/* FST_SPI_MISO_IO1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_101, NATIVE, DEEP, NF1),/* FST_IO2 - MEM_CONFIG0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_102, NATIVE, DEEP, NF1),/* FST_IO3 - MEM_CONFIG1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_103, NATIVE, DEEP, NF1),/* FST_SPI_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* FST_SPI_CLK_FB - Pad not bonded, default register value is the same</span><br><span style="color: hsl(120, 100%, 40%);">+ * as here. Refer to Intel Doc APL EDS Vol 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(FST_SPI_CLK_FB, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SIO_SPI_0 for F-module on mainboard */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_104, DN_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_105, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO_106 configured as XCS for TPM */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_106, UP_20K, DEEP, NF3),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_109, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_110, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SIO_SPI_1 -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_111, DN_20K, DEEP), /* GP_SSP_1_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_112, DN_20K, DEEP), /* GP_SSP_1_FS0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_113, DN_20K, DEEP), /* GP_SSP_1_FS1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_116, DN_20K, DEEP), /* GP_SSP_1_RXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_117, DN_20K, DEEP), /* GP_SSP_1_TXD */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SIO_SPI_2 -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_118, UP_20K, DEEP), /* GP_SSP_2_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_119, DN_20K, DEEP), /* GP_SSP_2_FS0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_120, DN_20K, DEEP), /* GP_SSP_2_FS1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_121, DN_20K, DEEP), /* GP_SSP_2_FS2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_122, DN_20K, DEEP), /* GP_SSP_2_RXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_123, DN_20K, DEEP), /* GP_SSP_2_TXD */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* North Community */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_0, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO_1 in early_gpio_table */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_2, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO_3,4 in early_gpio_table */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_5, DN_20K, DEEP), /* TRACE_0_DATA4_VNN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_6, DN_20K, DEEP), /* TRACE_0_DATA5_VNN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPIO_7, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_8, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_9, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_10, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_11, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_12, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_13, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_14, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_15, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_16, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_17, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_18, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_19, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_20, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPIO_21, 0, DEEP), /* activate SMARC Ethernetmac 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPIO_22, 0, DEEP), /* activate SMARC Ethernetmac 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_23, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_24, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_25, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_26, UP_20K, DEEP, NF5), /* SATA_LEDN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_27, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPIO_28, 1, DEEP), /* disable SMARC HDMI */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPIO_29, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_30, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_31, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_32, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_33, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_34, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_35, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_36, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_37, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_38, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_39, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_40, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* LPSS_UART[0:2] */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_41, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO_42/43 are in early_gpio_table */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_44, DN_20K, DEEP), /* LPSS_UART1_RTS - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_45, DN_20K, DEEP), /* LPSS_UART1_CTS - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO_46/47 are in early_gpio_table */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_48, DN_20K, DEEP), /* LPSS_UART2_RTS - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_49, DN_20K, DEEP), /* LPSS_UART2_CTS - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Camera interface -- completely unused. */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_62, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_63, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_64, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_65, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_66, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_67, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPIO_68, 0, DEEP), /* APL4 Testpoint P403 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPIO_69, 0, DEEP), /* APL4 Testpoint P404 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_70, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPIO_71, 1, DEEP), /* XCHC_UPD_REQ */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPIO_72, 0, DEEP), /* APL4 Testpoint P402 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_73, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* no TAP controller pins available on SMARC of APL4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(TCK, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(TRST_B, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(TMS, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(TDI, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(CX_PMODE, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(CX_PREQ_B, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(JTAGX, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(CX_PRDY_B, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(TDO, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO_[216:219] described into EDS Vol1. */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(CNV_BRI_DT, 0, DEEP), /* Disable eDP to LVDS bridge */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(CNV_BRI_RSP, UP_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(CNV_RGI_DT, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Writing to following GPIO registers leads to 0xFFFF FFFF in CFG0/1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(CNV_RGI_RSP, DN_20K, DEEP), /* pin open */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Serial Voltage Identification */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(SVID0_ALERT_B, NONE, DEEP, NF1), /* SVID0_ALERT_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(SVID0_DATA, UP_20K, DEEP, NF1), /* SVID0_DATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(SVID0_CLK, UP_20K, DEEP, NF1), /* SVID0_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config *variant_gpio_table(size_t *num)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *num = ARRAY_SIZE(gpio_table);</span><br><span style="color: hsl(120, 100%, 40%);">+ return gpio_table;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPIOs needed prior to ramstage. */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_config early_gpio_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Southwest Community */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Multiplexed I2C7 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(SMB_ALERTB, UP_20K, DEEP, NF2),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(SMB_CLK, UP_20K, DEEP, NF2),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(SMB_DATA, UP_20K, DEEP, NF2),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* get LPC Bus early working */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(LPC_CLKOUT1, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(LPC_FRAMEB, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* North Community */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPIO_1, 1, DEEP), /* XPCIE_A_RST */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPIO_3, 1, DEEP), /* XPCIE_B_RST */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPIO_4, 1, DEEP), /* XPCIE_C_RST */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* UARTs for early coreboot output */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_42, UP_20K, DEEP, NF1), /* LPSS_UART1_RXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_43, UP_20K, DEEP, NF1), /* LPSS_UART1_TXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_46, UP_20K, DEEP, NF1), /* LPSS_UART2_RXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_47, UP_20K, DEEP, NF1), /* LPSS_UART2_TXD */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config *variant_early_gpio_table(size_t *num)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *num = ARRAY_SIZE(early_gpio_table);</span><br><span style="color: hsl(120, 100%, 40%);">+ return early_gpio_table;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30128">change 30128</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30128"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: Ia69603f42c57c1cc682550b8eeeab42fbac27563 </div>
<div style="display:none"> Gerrit-Change-Number: 30128 </div>
<div style="display:none"> Gerrit-PatchSet: 7 </div>
<div style="display:none"> Gerrit-Owner: uwe poeche <uwe.poeche@siemens.com> </div>
<div style="display:none"> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer@siemens.com> </div>
<div style="display:none"> Gerrit-Reviewer: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Werner Zeh <werner.zeh@siemens.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-Reviewer: uwe poeche <uwe.poeche@siemens.com> </div>
<div style="display:none"> Gerrit-CC: HAOUAS Elyes <ehaouas@noos.fr> </div>
<div style="display:none"> Gerrit-MessageType: merged </div>