<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30245">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/kontron/986lcd-m: Implement disabling ethernet NIC in ramstage<br><br>With the i82801gx code automatically disabling devices ethernet<br>NICs attached to the southbridge PCIe ports can now be disabled<br>during the ramstage.<br><br>Change-Id: If4163f8101d37cc09c0b51b1be20bf8388ed2b89<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/mainboard/kontron/986lcd-m/mainboard.c<br>M src/mainboard/kontron/986lcd-m/romstage.c<br>2 files changed, 28 insertions(+), 47 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/30245/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c</span><br><span>index cc32b99..1f3df71 100644</span><br><span>--- a/src/mainboard/kontron/986lcd-m/mainboard.c</span><br><span>+++ b/src/mainboard/kontron/986lcd-m/mainboard.c</span><br><span>@@ -13,8 +13,10 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span> #include <types.h></span><br><span> #include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_def.h></span><br><span> #include <console/console.h></span><br><span> #include <drivers/intel/gma/int15.h></span><br><span> #include <pc80/mc146818rtc.h></span><br><span>@@ -157,6 +159,32 @@</span><br><span> hwm_setup();</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static void mainboard_init(void *chip_info)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int i;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 1; i <= 3; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ int ethernet_disable = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ char cmos_option_name[] = "ethernetx";</span><br><span style="color: hsl(120, 100%, 40%);">+ snprintf(cmos_option_name, sizeof(cmos_option_name),</span><br><span style="color: hsl(120, 100%, 40%);">+ "ethernet%01d", i);</span><br><span style="color: hsl(120, 100%, 40%);">+ get_option(ðernet_disable, cmos_option_name);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!ethernet_disable)</span><br><span style="color: hsl(120, 100%, 40%);">+ continue;</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Disabling Ethernet NIC #%d\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ dev = dev_find_slot(0, PCI_DEVFN(28, i - 1));</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev == NULL) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR,</span><br><span style="color: hsl(120, 100%, 40%);">+ "Disabling Ethernet NIC: Cannot find 00:1c.%d!\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ i - 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ continue;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ dev->enabled = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct chip_operations mainboard_ops = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .init = mainboard_init,</span><br><span> .enable_dev = mainboard_enable,</span><br><span> };</span><br><span>diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c</span><br><span>index e85135b..4e84d7a 100644</span><br><span>--- a/src/mainboard/kontron/986lcd-m/romstage.c</span><br><span>+++ b/src/mainboard/kontron/986lcd-m/romstage.c</span><br><span>@@ -166,8 +166,6 @@</span><br><span> </span><br><span> static void rcba_config(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32 = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Set up virtual channel 0 */</span><br><span> </span><br><span> /* Device 1f interrupt pin register */</span><br><span>@@ -185,50 +183,6 @@</span><br><span> /* Enable IOAPIC */</span><br><span> RCBA8(OIC) = 0x03;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Now, this is a bit ugly. As per PCI specification, function 0 of a</span><br><span style="color: hsl(0, 100%, 40%);">- * device always has to be implemented. So disabling ethernet port 1</span><br><span style="color: hsl(0, 100%, 40%);">- * would essentially disable all three ethernet ports of the mainboard.</span><br><span style="color: hsl(0, 100%, 40%);">- * It's possible to rename the ports to achieve compatibility to the</span><br><span style="color: hsl(0, 100%, 40%);">- * PCI spec but this will confuse all (static!) tables containing</span><br><span style="color: hsl(0, 100%, 40%);">- * interrupt routing information.</span><br><span style="color: hsl(0, 100%, 40%);">- * To avoid this, we enable (unused) port 6 and swap it with port 1</span><br><span style="color: hsl(0, 100%, 40%);">- * in the case that ethernet port 1 is disabled. Since no devices</span><br><span style="color: hsl(0, 100%, 40%);">- * are connected to that port, we don't have to worry about interrupt</span><br><span style="color: hsl(0, 100%, 40%);">- * routing.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- int port_shuffle = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable unused devices */</span><br><span style="color: hsl(0, 100%, 40%);">- if (read_option(ethernet1, 0) != 0) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Disabling ethernet adapter 1.\n");</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 |= FD_PCIE1;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- if (read_option(ethernet2, 0) != 0) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Disabling ethernet adapter 2.\n");</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 |= FD_PCIE2;</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- if (reg32 & FD_PCIE1)</span><br><span style="color: hsl(0, 100%, 40%);">- port_shuffle = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- if (read_option(ethernet3, 0) != 0) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Disabling ethernet adapter 3.\n");</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 |= FD_PCIE3;</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- if (reg32 & FD_PCIE1)</span><br><span style="color: hsl(0, 100%, 40%);">- port_shuffle = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (port_shuffle) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable PCIE6 again */</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 &= ~FD_PCIE6;</span><br><span style="color: hsl(0, 100%, 40%);">- /* Swap PCIE6 and PCIE1 */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(RPFN) = 0x00043215;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 |= 1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Enable PCIe Root Port Clock Gate */</span><br><span> </span><br><span> }</span><br><span>@@ -272,7 +226,6 @@</span><br><span> reg32 &= ~(3 << 0);</span><br><span> reg32 |= (1 << 0);</span><br><span> RCBA32(0x3430) = reg32;</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) |= (1 << 0);</span><br><span> RCBA16(0x0200) = 0x2008;</span><br><span> RCBA8(0x2027) = 0x0d;</span><br><span> RCBA16(0x3e08) |= (1 << 7);</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30245">change 30245</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: If4163f8101d37cc09c0b51b1be20bf8388ed2b89 </div>
<div style="display:none"> Gerrit-Change-Number: 30245 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>