<p>Nico Huber has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30246">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skl/graphics: Implement panel setup<br><br>Logs from Linux' i915 suggest that not even the FSP/GOP takes proper<br>care of this. The sequence is mostly the same as on older platforms,<br>with a slightly different configuration of the backlight PWM.<br><br>Change-Id: I762a77c8df023a4c14af502af5edfeeb961da1ae<br>Signed-off-by: Nico Huber <nico.h@gmx.de><br>---<br>M src/soc/intel/skylake/chip.h<br>M src/soc/intel/skylake/graphics.c<br>2 files changed, 76 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/30246/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h</span><br><span>index 7014a2e..fa41f71 100644</span><br><span>--- a/src/soc/intel/skylake/chip.h</span><br><span>+++ b/src/soc/intel/skylake/chip.h</span><br><span>@@ -44,6 +44,18 @@</span><br><span> /* Common struct containing soc config data required by common code */</span><br><span> struct soc_intel_common_config common_soc_config;</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ /* IGD panel configuration */</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned int gpu_pp_up_delay_ms;</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned int gpu_pp_down_delay_ms;</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned int gpu_pp_cycle_delay_ms;</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned int gpu_pp_backlight_on_delay_ms;</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned int gpu_pp_backlight_off_delay_ms;</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned int gpu_pch_backlight_pwm_hz;</span><br><span style="color: hsl(120, 100%, 40%);">+ enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ GPU_BACKLIGHT_POLARITY_HIGH = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ GPU_BACKLIGHT_POLARITY_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ } gpu_pch_backlight_polarity;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /*</span><br><span> * Interrupt Routing configuration</span><br><span> * If bit7 is 1, the interrupt is disabled.</span><br><span>diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c</span><br><span>index 33841b3..7a6b36a 100644</span><br><span>--- a/src/soc/intel/skylake/graphics.c</span><br><span>+++ b/src/soc/intel/skylake/graphics.c</span><br><span>@@ -16,8 +16,10 @@</span><br><span> </span><br><span> #include <bootmode.h></span><br><span> #include <cbmem.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <commonlib/helpers.h></span><br><span> #include <console/console.h></span><br><span> #include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/resource.h></span><br><span> #include <drivers/intel/gma/i915_reg.h></span><br><span> #include <drivers/intel/gma/libgfxinit.h></span><br><span> #include <intelblocks/graphics.h></span><br><span>@@ -30,10 +32,72 @@</span><br><span> return graphics_get_memory_base();</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static void graphics_setup_panel(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct soc_intel_skylake_config *conf = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct resource *mmio_res;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t *base;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!conf)</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mmio_res = find_resource(dev, PCI_BASE_ADDRESS_0);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!mmio_res || !mmio_res->base)</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+ base = (void *)(uintptr_t)mmio_res->base;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = conf->gpu_pp_up_delay_ms * 10 << 16;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 |= conf->gpu_pp_backlight_on_delay_ms * 10;</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(base + PCH_PP_ON_DELAYS, reg32);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = conf->gpu_pp_down_delay_ms * 10 << 16;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 |= conf->gpu_pp_backlight_off_delay_ms * 10;</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(base + PCH_PP_OFF_DELAYS, reg32);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = read32(base + PCH_PP_DIVISOR);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 &= ~0x1f;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 |= (DIV_ROUND_UP(conf->gpu_pp_cycle_delay_ms, 100) + 1) & 0x1f;</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(base + PCH_PP_DIVISOR, reg32);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* So far all devices seem to use the PCH PWM function.</span><br><span style="color: hsl(120, 100%, 40%);">+ The CPU PWM registers are all zero after reset. */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (conf->gpu_pch_backlight_pwm_hz) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Reference clock is 24MHz. We can choose either a 16</span><br><span style="color: hsl(120, 100%, 40%);">+ or a 128 step increment. Use 16 if we would have less</span><br><span style="color: hsl(120, 100%, 40%);">+ than 100 steps otherwise. */</span><br><span style="color: hsl(120, 100%, 40%);">+ const unsigned int hz_limit = 24 * 1000 * 1000 / 128 / 100;</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned int pwm_increment, pwm_period;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 south_chicken1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ south_chicken1 = read32(base + SOUTH_CHICKEN1);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (conf->gpu_pch_backlight_pwm_hz > hz_limit) {</span><br><span style="color: hsl(120, 100%, 40%);">+ pwm_increment = 16;</span><br><span style="color: hsl(120, 100%, 40%);">+ south_chicken1 &= ~1;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ pwm_increment = 128;</span><br><span style="color: hsl(120, 100%, 40%);">+ south_chicken1 |= 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(base + SOUTH_CHICKEN1, south_chicken1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pwm_period = 24 * 1000 * 1000 / pwm_increment</span><br><span style="color: hsl(120, 100%, 40%);">+ / conf->gpu_pch_backlight_pwm_hz;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Start with a 50% duty cycle. */</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(base + BLC_PWM_PCH_CTL2,</span><br><span style="color: hsl(120, 100%, 40%);">+ pwm_period << 16 | pwm_period / 2);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(base + BLC_PWM_PCH_CTL1,</span><br><span style="color: hsl(120, 100%, 40%);">+ !!conf->gpu_pch_backlight_polarity << 29 |</span><br><span style="color: hsl(120, 100%, 40%);">+ BLM_PCH_PWM_ENABLE);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void graphics_soc_init(struct device *dev)</span><br><span> {</span><br><span> u32 ddi_buf_ctl;</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ graphics_setup_panel(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /*</span><br><span> * Enable DDI-A (eDP) 4-lane operation if the link is not up yet.</span><br><span> * This will allow the kernel to use 4-lane eDP links properly</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30246">change 30246</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I762a77c8df023a4c14af502af5edfeeb961da1ae </div>
<div style="display:none"> Gerrit-Change-Number: 30246 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nico Huber <nico.h@gmx.de> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>