<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30244">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[WIP]sb/intel/i82801gx: Autodisable functions based on devicetree<br><br>This mostly reimplements what sandybridge does albeit a bit simpler<br><br>TODO:<br>- remove romstage FD<br>- What about INTLAN?<br><br>TESTED with coalescing (root port 0 disabled in devicetree)<br><br>Change-Id: I83576599538a02d295fe00b35826f98d8c97d1cf<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/southbridge/intel/i82801gx/i82801gx.c<br>M src/southbridge/intel/i82801gx/i82801gx.h<br>2 files changed, 205 insertions(+), 7 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/30244/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/intel/i82801gx/i82801gx.c b/src/southbridge/intel/i82801gx/i82801gx.c</span><br><span>index eb0583f..2541fc6 100644</span><br><span>--- a/src/southbridge/intel/i82801gx/i82801gx.c</span><br><span>+++ b/src/southbridge/intel/i82801gx/i82801gx.c</span><br><span>@@ -20,18 +20,204 @@</span><br><span> #include "i82801gx.h"</span><br><span> #include "sata.h"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static void ich_hide_devfn(unsigned int devfn)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (devfn) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVFN(27, 0): /* HD Audio Controller */</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32_OR(FD, FD_HDAUD);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32_OR(FD, ICH_DISABLE_PCIE(PCI_FUNC(devfn)));</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVFN(29, 0): /* UHCI #1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVFN(29, 1): /* UHCI #2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVFN(29, 2): /* UHCI #3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVFN(29, 3): /* UHCI #4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32_OR(FD, ICH_DISABLE_UHCI(PCI_FUNC(devfn)));</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVFN(29, 7): /* EHCI #1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32_OR(FD, FD_EHCI);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVFN(30, 2): /* AC Audio */</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32_OR(FD, FD_ACMOD);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVFN(30, 3): /* AC Modem */</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32_OR(FD, FD_ACMOD);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVFN(31, 0): /* LPC */</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32_OR(FD, FD_LPCB);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVFN(31, 1): /* PATA #1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32_OR(FD, FD_PATA);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVFN(31, 2): /* SATA #1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32_OR(FD, FD_PATA);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVFN(31, 3): /* SMBUS */</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32_OR(FD, FD_SMBUS);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* RPFN is a write-once register so keep a copy until it is written */</span><br><span style="color: hsl(120, 100%, 40%);">+static u32 new_rpfn;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Update devicetree with new Root Port function number assignment */</span><br><span style="color: hsl(120, 100%, 40%);">+static void ich_pcie_devicetree_update(</span><br><span style="color: hsl(120, 100%, 40%);">+ struct southbridge_intel_i82801gx_config *config)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Update the function numbers in the static devicetree */</span><br><span style="color: hsl(120, 100%, 40%);">+ for (dev = all_devices; dev; dev = dev->next) {</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 new_devfn;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Only care about ICH PCIe root ports */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (PCI_SLOT(dev->path.pci.devfn) != ICH_PCIE_DEV_SLOT)</span><br><span style="color: hsl(120, 100%, 40%);">+ continue;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Determine the new devfn for this port */</span><br><span style="color: hsl(120, 100%, 40%);">+ new_devfn = PCI_DEVFN(ICH_PCIE_DEV_SLOT,</span><br><span style="color: hsl(120, 100%, 40%);">+ RPFN_FNGET(new_rpfn,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_FUNC(dev->path.pci.devfn)));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev->path.pci.devfn != new_devfn) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG,</span><br><span style="color: hsl(120, 100%, 40%);">+ "ICH: PCIe map %02x.%1x -> %02x.%1x\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_SLOT(dev->path.pci.devfn),</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_FUNC(dev->path.pci.devfn),</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_SLOT(new_devfn), PCI_FUNC(new_devfn));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dev->path.pci.devfn = new_devfn;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Swap function numbers assigned to two PCIe Root Ports */</span><br><span style="color: hsl(120, 100%, 40%);">+static void ich_pcie_function_swap(u8 old_fn, u8 new_fn)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 old_rpfn = new_rpfn;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "ICH: Remap PCIe function %d to %d\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ old_fn, new_fn);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ new_rpfn &= ~(RPFN_FNMASK(old_fn) | RPFN_FNMASK(new_fn));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Old function set to new function and disabled */</span><br><span style="color: hsl(120, 100%, 40%);">+ new_rpfn |= RPFN_FNSET(old_fn, RPFN_FNGET(old_rpfn, new_fn));</span><br><span style="color: hsl(120, 100%, 40%);">+ new_rpfn |= RPFN_FNSET(new_fn, RPFN_FNGET(old_rpfn, old_fn));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Special handling for PCIe Root Port devices */</span><br><span style="color: hsl(120, 100%, 40%);">+static void ich_pcie_enable(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct southbridge_intel_i82801gx_config *config = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+ static int pcie_port_coalesce = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ static int port_coalescence_done = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!config)</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Save a copy of the Root Port Function Number map when</span><br><span style="color: hsl(120, 100%, 40%);">+ * starting to walk the list of PCIe Root Ports so it can</span><br><span style="color: hsl(120, 100%, 40%);">+ * be updated locally and written out when the last port</span><br><span style="color: hsl(120, 100%, 40%);">+ * has been processed.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (PCI_FUNC(dev->path.pci.devfn) == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ new_rpfn = RCBA32(RPFN);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enable Root Port coalescing if the first port is disabled</span><br><span style="color: hsl(120, 100%, 40%);">+ * or the other devices will not be enumerated by the OS.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!dev->enabled)</span><br><span style="color: hsl(120, 100%, 40%);">+ pcie_port_coalesce = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pcie_port_coalesce)</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO,</span><br><span style="color: hsl(120, 100%, 40%);">+ "ICH: PCIe Root Port coalescing is enabled\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!dev->enabled) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Ensure memory, io, and bus master are all disabled */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = pci_read_config32(dev, PCI_COMMAND);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 &= ~(PCI_COMMAND_MASTER |</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_COMMAND_MEMORY | PCI_COMMAND_IO);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(dev, PCI_COMMAND, reg32);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Hide this device if possible */</span><br><span style="color: hsl(120, 100%, 40%);">+ ich_hide_devfn(dev->path.pci.devfn);</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Check if there is a lower disabled port to swap with this</span><br><span style="color: hsl(120, 100%, 40%);">+ * port in order to maintain linear order starting at zero.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pcie_port_coalesce && !port_coalescence_done) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Swap places with this function */</span><br><span style="color: hsl(120, 100%, 40%);">+ ich_pcie_function_swap(PCI_FUNC(dev->path.pci.devfn),</span><br><span style="color: hsl(120, 100%, 40%);">+ 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ port_coalescence_done = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable SERR */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = pci_read_config32(dev, PCI_COMMAND);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 |= PCI_COMMAND_SERR;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(dev, PCI_COMMAND, reg32);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * When processing the last PCIe root port we can now</span><br><span style="color: hsl(120, 100%, 40%);">+ * update the Root Port Function Number and Hide register.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (PCI_FUNC(dev->path.pci.devfn) == 5) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "ICH: RPFN 0x%08x -> 0x%08x\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32(RPFN), new_rpfn);</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32(RPFN) = new_rpfn;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Update static devictree with new function numbers */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pcie_port_coalesce)</span><br><span style="color: hsl(120, 100%, 40%);">+ ich_pcie_devicetree_update(config);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void i82801gx_enable(struct device *dev)</span><br><span> {</span><br><span> u32 reg32;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable SERR */</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = pci_read_config32(dev, PCI_COMMAND);</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 |= PCI_COMMAND_SERR;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(dev, PCI_COMMAND, reg32);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ICH PCIe Root Ports get special handling */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (PCI_SLOT(dev->path.pci.devfn) == ICH_PCIE_DEV_SLOT)</span><br><span style="color: hsl(120, 100%, 40%);">+ return ich_pcie_enable(dev);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- if (dev->path.pci.devfn == PCI_DEVFN(31, 2)) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Set SATA mode early\n");</span><br><span style="color: hsl(0, 100%, 40%);">- sata_enable(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!dev->enabled) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Ensure memory, io, and bus master are all disabled */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = pci_read_config32(dev, PCI_COMMAND);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 &= ~(PCI_COMMAND_MASTER |</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_COMMAND_MEMORY | PCI_COMMAND_IO);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(dev, PCI_COMMAND, reg32);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Hide this device if possible */</span><br><span style="color: hsl(120, 100%, 40%);">+ ich_hide_devfn(dev->path.pci.devfn);</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable SERR */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = pci_read_config32(dev, PCI_COMMAND);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 |= PCI_COMMAND_SERR;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(dev, PCI_COMMAND, reg32);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev->path.pci.devfn == PCI_DEVFN(31, 2)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Set SATA mode early\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ sata_enable(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> }</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h</span><br><span>index 40c2bb7..c1235ed 100644</span><br><span>--- a/src/southbridge/intel/i82801gx/i82801gx.h</span><br><span>+++ b/src/southbridge/intel/i82801gx/i82801gx.h</span><br><span>@@ -72,6 +72,8 @@</span><br><span> #define SEE (1 << 1)</span><br><span> #define PERE (1 << 0)</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define ICH_PCIE_DEV_SLOT 28</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* PCI Configuration Space (D31:F0): LPC */</span><br><span> </span><br><span> #define SERIRQ_CNTL 0x64</span><br><span>@@ -231,6 +233,13 @@</span><br><span> #define RPC 0x0224 /* 32bit */</span><br><span> #define RPFN 0x0238 /* 32bit */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* Get the function number assigned to a Root Port */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RPFN_FNGET(reg, port) (((reg) >> ((port) * 4)) & 7)</span><br><span style="color: hsl(120, 100%, 40%);">+/* Set the function number for a Root Port */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RPFN_FNSET(port, func) (((func) & 7) << ((port) * 4))</span><br><span style="color: hsl(120, 100%, 40%);">+/* Root Port function number mask */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RPFN_FNMASK(port) (7 << ((port) * 4))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define TRSR 0x1e00 /* 8bit */</span><br><span> #define TRCR 0x1e10 /* 64bit */</span><br><span> #define TWDR 0x1e18 /* 64bit */</span><br><span>@@ -273,6 +282,7 @@</span><br><span> #define FD_PCIE3 (1 << 18)</span><br><span> #define FD_PCIE2 (1 << 17)</span><br><span> #define FD_PCIE1 (1 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ICH_DISABLE_PCIE(x) (1 << (16 + x))</span><br><span> #define FD_EHCI (1 << 15)</span><br><span> #define FD_LPCB (1 << 14)</span><br><span> </span><br><span>@@ -283,6 +293,8 @@</span><br><span> #define FD_UHCI34 ((1 << 10) | FD_UHCI4)</span><br><span> #define FD_UHCI234 ((1 << 9) | FD_UHCI3)</span><br><span> #define FD_UHCI1234 ((1 << 8) | FD_UHCI2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ICH_DISABLE_UHCI(x) (1 << (8 + x))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> </span><br><span> #define FD_INTLAN (1 << 7)</span><br><span> #define FD_ACMOD (1 << 6)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30244">change 30244</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I83576599538a02d295fe00b35826f98d8c97d1cf </div>
<div style="display:none"> Gerrit-Change-Number: 30244 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>