<p>Matt DeVillier has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30232">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: ensure ACPI opregion restored on S3 with GOP init<br><br>The Intel GMA ACPI opregion address needs to be set on S3 resume,<br>otherwise the Windows display driver fails to re-initialize correctly.<br>Fix by ensuring the address is set correctly regardless of display<br>init type used (GOP, VBIOS, or libgfxinit).<br><br>Test: build/boot on google/chell, ensure internal display functional<br>following S3 resume under Windows 10.<br><br>Change-Id: I38a7f3df476c878e7a78ee6543270d71463cb69d<br>Signed-off-by: Matt DeVillier <matt.devillier@gmail.com><br>---<br>M src/soc/intel/skylake/graphics.c<br>1 file changed, 14 insertions(+), 14 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/30232/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c</span><br><span>index 33841b3..76d86e1 100644</span><br><span>--- a/src/soc/intel/skylake/graphics.c</span><br><span>+++ b/src/soc/intel/skylake/graphics.c</span><br><span>@@ -53,23 +53,23 @@</span><br><span>          * In case of non-FSP solution, SoC need to select another</span><br><span>    * Kconfig to perform GFX initialization.</span><br><span>     */</span><br><span style="color: hsl(0, 100%, 40%);">-     if (IS_ENABLED(CONFIG_RUN_FSP_GOP))</span><br><span style="color: hsl(0, 100%, 40%);">-             return;</span><br><span style="color: hsl(120, 100%, 40%);">+       if (!IS_ENABLED(CONFIG_RUN_FSP_GOP)) {</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-      /* IGD needs to Bus Master */</span><br><span style="color: hsl(0, 100%, 40%);">-   u32 reg32 = pci_read_config32(dev, PCI_COMMAND);</span><br><span style="color: hsl(0, 100%, 40%);">-        reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;</span><br><span style="color: hsl(0, 100%, 40%);">-      pci_write_config32(dev, PCI_COMMAND, reg32);</span><br><span style="color: hsl(120, 100%, 40%);">+          /* IGD needs to Bus Master */</span><br><span style="color: hsl(120, 100%, 40%);">+         u32 reg32 = pci_read_config32(dev, PCI_COMMAND);</span><br><span style="color: hsl(120, 100%, 40%);">+              reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;</span><br><span style="color: hsl(120, 100%, 40%);">+            pci_write_config32(dev, PCI_COMMAND, reg32);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-        if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) {</span><br><span style="color: hsl(0, 100%, 40%);">-              if (!acpi_is_wakeup_s3() && display_init_required()) {</span><br><span style="color: hsl(0, 100%, 40%);">-                  int lightup_ok;</span><br><span style="color: hsl(0, 100%, 40%);">-                 gma_gfxinit(&lightup_ok);</span><br><span style="color: hsl(0, 100%, 40%);">-                   gfx_set_init_done(lightup_ok);</span><br><span style="color: hsl(120, 100%, 40%);">+                if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) {</span><br><span style="color: hsl(120, 100%, 40%);">+                    if (!acpi_is_wakeup_s3() && display_init_required()) {</span><br><span style="color: hsl(120, 100%, 40%);">+                                int lightup_ok;</span><br><span style="color: hsl(120, 100%, 40%);">+                               gma_gfxinit(&lightup_ok);</span><br><span style="color: hsl(120, 100%, 40%);">+                         gfx_set_init_done(lightup_ok);</span><br><span style="color: hsl(120, 100%, 40%);">+                        }</span><br><span style="color: hsl(120, 100%, 40%);">+             } else {</span><br><span style="color: hsl(120, 100%, 40%);">+                      /* Initialize PCI device, load/execute BIOS Option ROM */</span><br><span style="color: hsl(120, 100%, 40%);">+                     pci_dev_init(dev);</span><br><span>           }</span><br><span style="color: hsl(0, 100%, 40%);">-       } else {</span><br><span style="color: hsl(0, 100%, 40%);">-                /* Initialize PCI device, load/execute BIOS Option ROM */</span><br><span style="color: hsl(0, 100%, 40%);">-               pci_dev_init(dev);</span><br><span>   }</span><br><span> </span><br><span>        intel_gma_restore_opregion();</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30232">change 30232</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="htt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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I38a7f3df476c878e7a78ee6543270d71463cb69d </div>
<div style="display:none"> Gerrit-Change-Number: 30232 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>