<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30211">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: SATA and DMI power optimize<br><br>Expose the FSP interface to enable SATA and PCH side DMI power optimize<br>options. Actual step exectued in FSP, step defined in cannonlake pch<br>BIOS spec(CDI# 570374).<br><br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>Change-Id: Ic0c589bb21e56800090bc0c75a0256a0409efc78<br>---<br>M src/soc/intel/cannonlake/chip.h<br>M src/soc/intel/cannonlake/fsp_params.c<br>2 files changed, 10 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/30211/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h</span><br><span>index 9eb91bd..a2e0915 100644</span><br><span>--- a/src/soc/intel/cannonlake/chip.h</span><br><span>+++ b/src/soc/intel/cannonlake/chip.h</span><br><span>@@ -263,6 +263,12 @@</span><br><span>   /* Intel VT configuration */</span><br><span>         uint8_t VtdDisable;</span><br><span>  uint8_t VmxEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+  /* DMI Power Optimizer */</span><br><span style="color: hsl(120, 100%, 40%);">+     uint8_t dmipwroptimize;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+     /* SATA Power Optimizer */</span><br><span style="color: hsl(120, 100%, 40%);">+    uint8_t satapwroptimize;</span><br><span> };</span><br><span> </span><br><span> typedef struct soc_intel_cannonlake_config config_t;</span><br><span>diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c</span><br><span>index f957459..875c871 100644</span><br><span>--- a/src/soc/intel/cannonlake/fsp_params.c</span><br><span>+++ b/src/soc/intel/cannonlake/fsp_params.c</span><br><span>@@ -210,6 +210,10 @@</span><br><span>    * 3 = GT unsliced,  4 = GT sliced */</span><br><span>        for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++)</span><br><span>             fill_vr_domain_config(params, i, &config->domain_vr_config[i]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+      /* Power Optimizer */</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PchPwrOptEnable = config->dmipwroptimize;</span><br><span style="color: hsl(120, 100%, 40%);">+       params->SataPwrOptEnable = config->satapwroptimize;</span><br><span> }</span><br><span> </span><br><span> /* Mainboard GPIO Configuration */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30211">change 30211</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30211"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: Ic0c589bb21e56800090bc0c75a0256a0409efc78 </div>
<div style="display:none"> Gerrit-Change-Number: 30211 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>