<p>Bora Guvendik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30176">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[WIP]mb/google/octopus: Override emmc DLL values for Bobba<br><br>New emmc DLL values for Bobba.<br><br>BUG=b:120561055<br>TEST=Boot to OS, chromeos-install, mmc_test<br><br>Change-Id: I5a0d9587a91b3c71c042cd8ea360c816ea29fb91<br>Signed-off-by: Bora Guvendik <bora.guvendik@intel.com><br>---<br>M src/mainboard/google/octopus/variants/bobba/overridetree.cb<br>1 file changed, 41 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/30176/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/octopus/variants/bobba/overridetree.cb b/src/mainboard/google/octopus/variants/bobba/overridetree.cb</span><br><span>index c0f37e2..17686f6 100644</span><br><span>--- a/src/mainboard/google/octopus/variants/bobba/overridetree.cb</span><br><span>+++ b/src/mainboard/google/octopus/variants/bobba/overridetree.cb</span><br><span>@@ -1,5 +1,46 @@</span><br><span> chip soc/intel/apollolake</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ # EMMC Tx CMD Delay</span><br><span style="color: hsl(120, 100%, 40%);">+ # Refer to EDS-Vol2-16.32.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [14:8] steps of delay for DDR mode, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [6:0] steps of delay for SDR mode, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "emmc_tx_cmd_cntl" = "0x505"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # EMMC TX DATA Delay 1</span><br><span style="color: hsl(120, 100%, 40%);">+ # Refer to EDS-Vol2-16.33.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [14:8] steps of delay for HS400, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [6:0] steps of delay for SDR104/HS200, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "emmc_tx_data_cntl1" = "0x0a0b"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # EMMC TX DATA Delay 2</span><br><span style="color: hsl(120, 100%, 40%);">+ # Refer to EDS-Vol2-16.34.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [30:24] steps of delay for SDR50, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [22:16] steps of delay for DDR50, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [14:8] steps of delay for SDR25/HS50, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [6:0] steps of delay for SDR12, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "emmc_tx_data_cntl2" = "0x1c272828"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # EMMC RX CMD/DATA Delay 1</span><br><span style="color: hsl(120, 100%, 40%);">+ # Refer to EDS-Vol2-16.35.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [30:24] steps of delay for SDR50, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [22:16] steps of delay for DDR50, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [14:8] steps of delay for SDR25/HS50, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [6:0] steps of delay for SDR12, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "emmc_rx_cmd_data_cntl1" = "0x00181b1a"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # EMMC RX CMD/DATA Delay 2</span><br><span style="color: hsl(120, 100%, 40%);">+ # Refer to EDS-Vol2-16.37.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [17:16] stands for Rx Clock before Output Buffer</span><br><span style="color: hsl(120, 100%, 40%);">+ # [14:8] steps of delay for Auto Tuning Mode, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [6:0] steps of delay for HS200, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "emmc_rx_cmd_data_cntl2" = "0x10021"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # EMMC Rx Strobe Delay</span><br><span style="color: hsl(120, 100%, 40%);">+ # Refer to EDS-Vol2-16.36.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "emmc_rx_strobe_cntl" = "0x0a0a"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> # Intel Common SoC Config</span><br><span> #+-------------------+---------------------------+</span><br><span> #| Field | Value |</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30176">change 30176</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I5a0d9587a91b3c71c042cd8ea360c816ea29fb91 </div>
<div style="display:none"> Gerrit-Change-Number: 30176 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Bora Guvendik <bora.guvendik@intel.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>