<p>HAOUAS Elyes has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30195">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">northbridge: Remove unneeded include <pc80/mc146818rtc.h><br><br>Change-Id: Icae59721db530572d76035975a4e90686bf4fa65<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/northbridge/amd/amdfam10/link_control.c<br>M src/northbridge/amd/amdfam10/misc_control.c<br>M src/northbridge/amd/amdfam10/nb_control.c<br>M src/northbridge/amd/amdfam10/northbridge.c<br>M src/northbridge/intel/haswell/raminit.c<br>M src/northbridge/intel/pineview/raminit.c<br>M src/northbridge/intel/x4x/raminit.c<br>M src/northbridge/intel/x4x/raminit_ddr23.c<br>M src/northbridge/via/vx900/lpc.c<br>9 files changed, 0 insertions(+), 9 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/30195/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/amd/amdfam10/link_control.c b/src/northbridge/amd/amdfam10/link_control.c</span><br><span>index f82f238..504e187 100644</span><br><span>--- a/src/northbridge/amd/amdfam10/link_control.c</span><br><span>+++ b/src/northbridge/amd/amdfam10/link_control.c</span><br><span>@@ -23,7 +23,6 @@</span><br><span> #include <device/pci.h></span><br><span> #include <device/pci_ids.h></span><br><span> #include <device/pci_ops.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <pc80/mc146818rtc.h></span><br><span> #include <cpu/amd/model_10xxx_rev.h></span><br><span> </span><br><span> #include "amdfam10.h"</span><br><span>diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c</span><br><span>index 8323c1e..8cd32df 100644</span><br><span>--- a/src/northbridge/amd/amdfam10/misc_control.c</span><br><span>+++ b/src/northbridge/amd/amdfam10/misc_control.c</span><br><span>@@ -28,7 +28,6 @@</span><br><span> #include <device/pci.h></span><br><span> #include <device/pci_ids.h></span><br><span> #include <device/pci_ops.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <pc80/mc146818rtc.h></span><br><span> #include <lib.h></span><br><span> #include <cbmem.h></span><br><span> #include <cpu/amd/model_10xxx_rev.h></span><br><span>diff --git a/src/northbridge/amd/amdfam10/nb_control.c b/src/northbridge/amd/amdfam10/nb_control.c</span><br><span>index 255948d..a9bdb18 100644</span><br><span>--- a/src/northbridge/amd/amdfam10/nb_control.c</span><br><span>+++ b/src/northbridge/amd/amdfam10/nb_control.c</span><br><span>@@ -23,7 +23,6 @@</span><br><span> #include <device/pci.h></span><br><span> #include <device/pci_ids.h></span><br><span> #include <device/pci_ops.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <pc80/mc146818rtc.h></span><br><span> #include <cpu/amd/model_10xxx_rev.h></span><br><span> </span><br><span> #include "amdfam10.h"</span><br><span>diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c</span><br><span>index 4da5228..7f6c0f9 100644</span><br><span>--- a/src/northbridge/amd/amdfam10/northbridge.c</span><br><span>+++ b/src/northbridge/amd/amdfam10/northbridge.c</span><br><span>@@ -37,7 +37,6 @@</span><br><span> </span><br><span> #if IS_ENABLED(CONFIG_LOGICAL_CPUS)</span><br><span> #include <cpu/amd/multicore.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <pc80/mc146818rtc.h></span><br><span> #endif</span><br><span> </span><br><span> #include "northbridge.h"</span><br><span>diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c</span><br><span>index 221d71f..faaa9d0 100644</span><br><span>--- a/src/northbridge/intel/haswell/raminit.c</span><br><span>+++ b/src/northbridge/intel/haswell/raminit.c</span><br><span>@@ -23,7 +23,6 @@</span><br><span> #include <ip_checksum.h></span><br><span> #include <memory_info.h></span><br><span> #include <mrc_cache.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <pc80/mc146818rtc.h></span><br><span> #include <device/pci_def.h></span><br><span> #include <device/dram/ddr3.h></span><br><span> #include <smbios.h></span><br><span>diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c</span><br><span>index f199d9b..512403f 100644</span><br><span>--- a/src/northbridge/intel/pineview/raminit.c</span><br><span>+++ b/src/northbridge/intel/pineview/raminit.c</span><br><span>@@ -22,7 +22,6 @@</span><br><span> #include <lib.h></span><br><span> #include "pineview.h"</span><br><span> #include "raminit.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include <pc80/mc146818rtc.h></span><br><span> #include <spd.h></span><br><span> #include <string.h></span><br><span> </span><br><span>diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c</span><br><span>index c97c139..b3b84d8 100644</span><br><span>--- a/src/northbridge/intel/x4x/raminit.c</span><br><span>+++ b/src/northbridge/intel/x4x/raminit.c</span><br><span>@@ -29,7 +29,6 @@</span><br><span> #include <southbridge/intel/i82801jx/i82801jx.h> /* smbus_read_byte */</span><br><span> #endif</span><br><span> #include "x4x.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include <pc80/mc146818rtc.h></span><br><span> #include <spd.h></span><br><span> #include <string.h></span><br><span> #include <device/dram/ddr2.h></span><br><span>diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c</span><br><span>index 32fa0d9..5c5dafa 100644</span><br><span>--- a/src/northbridge/intel/x4x/raminit_ddr23.c</span><br><span>+++ b/src/northbridge/intel/x4x/raminit_ddr23.c</span><br><span>@@ -20,7 +20,6 @@</span><br><span> #include <console/console.h></span><br><span> #include <commonlib/helpers.h></span><br><span> #include <delay.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <pc80/mc146818rtc.h></span><br><span> #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)</span><br><span> #include <southbridge/intel/i82801gx/i82801gx.h></span><br><span> #else</span><br><span>diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c</span><br><span>index b9dac56..27e2384 100644</span><br><span>--- a/src/northbridge/via/vx900/lpc.c</span><br><span>+++ b/src/northbridge/via/vx900/lpc.c</span><br><span>@@ -20,7 +20,6 @@</span><br><span> #include <device/pci.h></span><br><span> #include <device/pci_ids.h></span><br><span> #include <pc80/i8259.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <pc80/mc146818rtc.h></span><br><span> #include <drivers/generic/ioapic/chip.h></span><br><span> </span><br><span> #include "vx900.h"</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30195">change 30195</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30195"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: Icae59721db530572d76035975a4e90686bf4fa65 </div>
<div style="display:none"> Gerrit-Change-Number: 30195 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: HAOUAS Elyes <ehaouas@noos.fr> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>