<p>Patrick Georgi <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30091">View Change</a></p><div style="white-space:pre-wrap">Approvals:
  build bot (Jenkins): Verified
  Bora Guvendik: Looks good to me, approved
  Roy Mingi Park: Looks good to me, but someone else must approve

</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/sarien: Disable unused SATA ports<br><br>Disable SATA port 0 and port 1 as that's not used as SATA on platform.<br><br>BUG=N/A<br>TEST=Build and boot up fine on google arcada board.<br><br>Change-Id: I1b8801f7a0f9b7847b85d7c315fa0a2093b32f70<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>Reviewed-on: https://review.coreboot.org/c/30091<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com><br>Reviewed-by: Bora Guvendik <bora.guvendik@intel.com><br>---<br>M src/mainboard/google/sarien/variants/arcada/devicetree.cb<br>1 file changed, 0 insertions(+), 4 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb</span><br><span>index 924f51d..ed2c34c 100644</span><br><span>--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb</span><br><span>+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb</span><br><span>@@ -18,11 +18,7 @@</span><br><span>      register "HeciEnabled" = "1"</span><br><span>     register "SataSalpSupport" = "1"</span><br><span>         register "SataMode" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">-   register "SataPortsEnable[0]" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">- register "SataPortsEnable[1]" = "1"</span><br><span>      register "SataPortsEnable[2]" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "SataPortsDevSlp[0]" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">- register "SataPortsDevSlp[1]" = "1"</span><br><span>      register "SataPortsDevSlp[2]" = "1"</span><br><span>      register "InternalGfx" = "1"</span><br><span>     register "SkipExtGfxScan" = "1"</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30091">change 30091</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30091"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I1b8801f7a0f9b7847b85d7c315fa0a2093b32f70 </div>
<div style="display:none"> Gerrit-Change-Number: 30091 </div>
<div style="display:none"> Gerrit-PatchSet: 2 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Bora Guvendik <bora.guvendik@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Lijian Zhao <lijian.zhao@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Roy Mingi Park <roy.mingi.park@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-MessageType: merged </div>