<p>Patrick Georgi <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30096">View Change</a></p><div style="white-space:pre-wrap">Approvals:
  build bot (Jenkins): Verified
  Bora Guvendik: Looks good to me, approved

</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/sarien: Disable PCH Gigabit LAN<br><br>There's no LAN connection on Arcada board, so disable PCH GBE.<br><br>BUG=N/A<br><br>Change-Id: I07c66df50dbe9fefd95a67b5af9e3f61ce6a18aa<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>Reviewed-on: https://review.coreboot.org/c/30096<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Bora Guvendik <bora.guvendik@intel.com><br>---<br>M src/mainboard/google/sarien/variants/arcada/devicetree.cb<br>1 file changed, 1 insertion(+), 6 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb</span><br><span>index fccec9f..924f51d 100644</span><br><span>--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb</span><br><span>+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb</span><br><span>@@ -78,11 +78,6 @@</span><br><span>            },</span><br><span>   }"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-     # PCIe port 9 for LAN</span><br><span style="color: hsl(0, 100%, 40%);">-   register "PcieRpEnable[8]" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">-    register "PcieClkSrcUsage[0]" = "PCIE_CLK_LAN"</span><br><span style="color: hsl(0, 100%, 40%);">-      register "PcieClkSrcClkReq[0]" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span>     # PCIe port 10 for M.2 2230 WLAN</span><br><span>     register "PcieRpEnable[9]" = "1"</span><br><span>         register "PcieClkSrcUsage[2]" = "9"</span><br><span>@@ -250,6 +245,6 @@</span><br><span>                device pci 1f.3 on  end # Intel HDA</span><br><span>          device pci 1f.4 on  end # SMBus</span><br><span>              device pci 1f.5 on  end # PCH SPI</span><br><span style="color: hsl(0, 100%, 40%);">-               device pci 1f.6 on  end # GbE</span><br><span style="color: hsl(120, 100%, 40%);">+         device pci 1f.6 off end # GbE</span><br><span>        end</span><br><span> end</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30096">change 30096</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30096"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I07c66df50dbe9fefd95a67b5af9e3f61ce6a18aa </div>
<div style="display:none"> Gerrit-Change-Number: 30096 </div>
<div style="display:none"> Gerrit-PatchSet: 5 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Bora Guvendik <bora.guvendik@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Lijian Zhao <lijian.zhao@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Roy Mingi Park <roy.mingi.park@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-MessageType: merged </div>