<p>Duncan Laurie has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30134">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Fix CNL-H GPIO pin map<br><br>The GPIO pin map for CNL-H does not match with the OS expected<br>pin numbers. This has been updated to match what is used by the<br>Linux kernel pinctrl driver and the pad base has been set for<br>the GPIO groups to match the sparse GPIO map used by the kernel.<br><br>I do not have CNL-H hardware to test this so it is verified against<br>the kernel driver at drivers/pinctrl/intel/pinctrl-cannonlake.c<br><br>Change-Id: Ife7d3090d654b0b88c6911befa08bf6abd4f2ff9<br>Signed-off-by: Duncan Laurie <dlaurie@google.com><br>---<br>M src/soc/intel/cannonlake/gpio_cnp_h.c<br>M src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h<br>2 files changed, 340 insertions(+), 224 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/30134/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/gpio_cnp_h.c b/src/soc/intel/cannonlake/gpio_cnp_h.c</span><br><span>index 939a38e..f03452e 100644</span><br><span>--- a/src/soc/intel/cannonlake/gpio_cnp_h.c</span><br><span>+++ b/src/soc/intel/cannonlake/gpio_cnp_h.c</span><br><span>@@ -32,38 +32,58 @@</span><br><span> { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },</span><br><span> };</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * The GPIO driver for Cannonlake on Windows/Linux expects 32 GPIOs per pad</span><br><span style="color: hsl(120, 100%, 40%);">+ * group, regardless of whether or not there is a physical pad for each</span><br><span style="color: hsl(120, 100%, 40%);">+ * exposed GPIO number.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This results in the OS having a sparse GPIO map, and devices that need</span><br><span style="color: hsl(120, 100%, 40%);">+ * to export an ACPI GPIO must use the OS expected number.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Not all pins are usable as GPIO and those groups do not have a pad base.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This layout matches the Linux kernel pinctrl map for CNL-H at:</span><br><span style="color: hsl(120, 100%, 40%);">+ * linux/drivers/pinctrl/intel/pinctrl-cannonlake.c</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span> static const struct pad_group cnl_community0_groups[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_A0, GPP_A0, GPP_A23), /* GPP_A */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_A0, GPP_B0, GPP_B23), /* GPP_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP_BASE(GPP_A0, GPP_A0, GPIO_RSVD_0, 0), /* GPP_A */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP_BASE(GPP_A0, GPP_B0, GPIO_RSVD_2, 32), /* GPP_B */</span><br><span> };</span><br><span> </span><br><span> static const struct pad_group cnl_community1_groups[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP_C */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_C0, GPP_D0, GPP_D23), /* GPP_D */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_C0, GPP_G0, GPP_G7), /* GPP_G */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 64), /* GPP_C */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP_BASE(GPP_C0, GPP_D0, GPP_D23, 96), /* GPP_D */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP_BASE(GPP_C0, GPP_G0, GPP_G7, 128), /* GPP_G */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_C0, GPIO_RSVD_3, GPIO_RSVD_10), /* AZA */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP_BASE(GPP_C0, GPIO_RSVD_11, GPIO_RSVD_42, 160),/* VGPIO_0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_C0, GPIO_RSVD_43, GPIO_RSVD_50), /* VGPIO_0 */</span><br><span> };</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* This community is not visible to the OS */</span><br><span> static const struct pad_group cnl_community2_groups[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPD0, GPD0, GPD11), /* GPD */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPD0, GPD0, GPD11), /* GPD */</span><br><span> };</span><br><span> </span><br><span> static const struct pad_group cnl_community3_groups[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_K0, GPP_K0, GPP_K23), /* GPP_K*/</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_K0, GPP_H0, GPP_H23), /* GPP_H */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_K0, GPP_E0, GPP_E12), /* GPP_E */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_K0, GPP_F0, GPP_F23), /* GPP_F */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP_BASE(GPP_K0, GPP_K0, GPP_K23, 192), /* GPP_K */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP_BASE(GPP_K0, GPP_H0, GPP_H23, 224), /* GPP_H */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP_BASE(GPP_K0, GPP_E0, GPP_E12, 256), /* GPP_E */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP_BASE(GPP_K0, GPP_F0, GPP_F23, 288), /* GPP_F */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_K0, GPIO_RSVD_51, GPIO_RSVD_59), /* SPI */</span><br><span> };</span><br><span> </span><br><span> static const struct pad_group cnl_community4_groups[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_I0, GPP_I0, GPP_I14), /* GPP_I */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_I0, GPP_J0, GPP_J11), /* GPP_J */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_RSVD_60, GPIO_RSVD_60, GPIO_RSVD_70), /* CPU */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_RSVD_60, GPIO_RSVD_71, GPIO_RSVD_79), /* JTAG */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP_BASE(GPP_RSVD_60, GPP_I0, GPP_I14, 320), /* GPP_I */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP_BASE(GPP_RSVD_60, GPP_J0, GPP_J11, 352), /* GPP_J */</span><br><span> };</span><br><span> </span><br><span> static const struct pad_community cnl_communities[] = {</span><br><span> { /* GPP A, B */</span><br><span> .port = PID_GPIOCOM0,</span><br><span> .first_pad = GPP_A0,</span><br><span style="color: hsl(0, 100%, 40%);">- .last_pad = GPP_B23,</span><br><span style="color: hsl(120, 100%, 40%);">+ .last_pad = GPIO_RSVD_2,</span><br><span> .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,</span><br><span> .pad_cfg_base = PAD_CFG_BASE,</span><br><span> .host_own_reg_0 = HOSTSW_OWN_REG_0,</span><br><span>@@ -79,7 +99,7 @@</span><br><span> }, { /* GPP C, D, G */</span><br><span> .port = PID_GPIOCOM1,</span><br><span> .first_pad = GPP_C0,</span><br><span style="color: hsl(0, 100%, 40%);">- .last_pad = GPP_G7,</span><br><span style="color: hsl(120, 100%, 40%);">+ .last_pad = GPP_RSVD_50,</span><br><span> .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,</span><br><span> .pad_cfg_base = PAD_CFG_BASE,</span><br><span> .host_own_reg_0 = HOSTSW_OWN_REG_0,</span><br><span>@@ -111,7 +131,7 @@</span><br><span> }, { /* GPP K, H, E, F */</span><br><span> .port = PID_GPIOCOM3,</span><br><span> .first_pad = GPP_K0,</span><br><span style="color: hsl(0, 100%, 40%);">- .last_pad = GPP_F23,</span><br><span style="color: hsl(120, 100%, 40%);">+ .last_pad = GPIO_RSVD_59,</span><br><span> .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,</span><br><span> .pad_cfg_base = PAD_CFG_BASE,</span><br><span> .host_own_reg_0 = HOSTSW_OWN_REG_0,</span><br><span>@@ -126,7 +146,7 @@</span><br><span> .num_groups = ARRAY_SIZE(cnl_community3_groups),</span><br><span> }, { /* GPP I, J */</span><br><span> .port = PID_GPIOCOM4,</span><br><span style="color: hsl(0, 100%, 40%);">- .first_pad = GPP_I0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .first_pad = GPIO_RSVD_60,</span><br><span> .last_pad = GPP_J11,</span><br><span> .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,</span><br><span> .pad_cfg_base = PAD_CFG_BASE,</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h</span><br><span>index 203632d..95f7e41 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h</span><br><span>@@ -66,242 +66,338 @@</span><br><span> #define GPP_A21 21</span><br><span> #define GPP_A22 22</span><br><span> #define GPP_A23 23</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_0 24</span><br><span> </span><br><span> /* Group B */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B0 24</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B1 25</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B2 26</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B3 27</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B4 28</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B5 29</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B6 30</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B7 31</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B8 32</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B9 33</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B10 34</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B11 35</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B12 36</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B13 37</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B14 38</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B15 39</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B16 40</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B17 41</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B18 42</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B19 43</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B20 44</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B21 45</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B22 46</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B23 47</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B0 25</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B1 26</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B2 27</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B3 28</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B4 29</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B5 30</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B6 31</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B7 32</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B8 33</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B9 34</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B10 35</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B11 36</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B12 37</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B13 38</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B14 39</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B15 40</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B16 41</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B17 42</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B18 43</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B19 44</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B20 45</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B21 46</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B22 47</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B23 48</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_1 49</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_2 50</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define NUM_GPIO_COM0_PADS (GPP_B23 - GPP_A0 + 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define NUM_GPIO_COM0_PADS (GPIO_RSVD_2 - GPP_A0 + 1)</span><br><span> </span><br><span> /* Group C */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C0 48</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C1 49</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C2 50</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C3 51</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C4 52</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C5 53</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C6 54</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C7 55</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C8 56</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C9 57</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C10 58</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C11 59</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C12 60</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C13 61</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C14 62</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C15 63</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C16 64</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C17 65</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C18 66</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C19 67</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C20 68</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C21 69</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C22 70</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C23 71</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C0 51</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C1 52</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C2 53</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C3 54</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C4 55</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C5 56</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C6 57</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C7 58</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C8 59</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C9 60</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C10 61</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C11 62</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C12 63</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C13 64</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C14 65</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C15 66</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C16 67</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C17 68</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C18 69</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C19 70</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C20 71</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C21 72</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C22 73</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C23 74</span><br><span> </span><br><span> /* Group D */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D0 72</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D1 73</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D2 74</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D3 75</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D4 76</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D5 77</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D6 78</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D7 79</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D8 80</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D9 81</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D10 82</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D11 83</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D12 84</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D13 85</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D14 86</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D15 87</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D16 88</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D17 89</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D18 90</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D19 91</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D20 92</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D21 93</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D22 94</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D23 95</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D0 75</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D1 76</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D2 77</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D3 78</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D4 79</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D5 80</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D6 81</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D7 82</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D8 83</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D9 84</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D10 85</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D11 86</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D12 87</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D13 88</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D14 89</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D15 90</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D16 91</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D17 92</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D18 93</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D19 94</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D20 95</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D21 96</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D22 97</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D23 98</span><br><span> </span><br><span> /* Group G */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G0 96</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G1 97</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G2 98</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G3 99</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G4 100</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G5 101</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G6 102</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G7 103</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G0 99</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G1 100</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G2 101</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G3 102</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G4 103</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G5 104</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G6 105</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G7 106</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define NUM_GPIO_COM1_PADS (GPP_G7 - GPP_C0 + 1)</span><br><span style="color: hsl(120, 100%, 40%);">+/* AZA */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_3 107</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_4 108</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_5 109</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_6 110</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_7 111</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_8 112</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_9 113</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_10 114</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* VGPIO_0 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_11 115</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_12 116</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_13 117</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_14 118</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_15 119</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_16 120</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_17 121</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_18 122</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_19 123</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_20 124</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_21 125</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_22 126</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_23 127</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_24 128</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_25 129</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_26 130</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_27 131</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_28 132</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_29 133</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_30 134</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_31 135</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_32 136</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_33 137</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_34 138</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_35 139</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_36 140</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_37 141</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_38 142</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_39 143</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_40 144</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_41 145</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_42 146</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* VGPIO_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_43 147</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_44 148</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_45 149</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_46 150</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_47 151</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_48 152</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_49 153</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_50 154</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define NUM_GPIO_COM1_PADS (GPIO_RSVD_50 - GPP_C0 + 1)</span><br><span> </span><br><span> /* Group K */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_K0 104</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_K1 105</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_K2 106</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_K3 107</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_K4 108</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_K5 109</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_K6 110</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_K7 111</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_K8 112</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_K9 113</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_K10 114</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_K11 115</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_K12 116</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_K13 117</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_K14 118</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_K15 119</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_K16 120</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_K17 121</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_K18 122</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_K19 123</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_K20 124</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_K21 125</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_K22 126</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_K23 127</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K0 155</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K1 156</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K2 157</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K3 158</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K4 159</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K5 160</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K6 161</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K7 162</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K8 163</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K9 164</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K10 165</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K11 166</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K12 167</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K13 168</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K14 169</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K15 170</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K16 171</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K17 172</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K18 173</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K19 174</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K20 175</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K21 176</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K22 177</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K23 178</span><br><span> </span><br><span> /* Group H */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H0 128</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H1 129</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H2 130</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H3 131</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H4 132</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H5 133</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H6 134</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H7 135</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H8 136</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H9 137</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H10 138</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H11 139</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H12 140</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H13 141</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H14 142</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H15 143</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H16 144</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H17 145</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H18 146</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H19 147</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H20 148</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H21 149</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H22 150</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H23 151</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H0 179</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H1 180</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H2 181</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H3 182</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H4 183</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H5 184</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H6 185</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H7 186</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H8 187</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H9 188</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H10 189</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H11 190</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H12 191</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H13 192</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H14 193</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H15 194</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H16 195</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H17 196</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H18 197</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H19 198</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H20 199</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H21 200</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H22 201</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H23 202</span><br><span> </span><br><span> /* Group E */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E0 152</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E1 153</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E2 154</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E3 155</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E4 156</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E5 157</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E6 158</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E7 159</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E8 160</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E9 161</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E10 162</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E11 163</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E12 164</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E0 203</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E1 204</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E2 205</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E3 206</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E4 207</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E5 208</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E6 209</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E7 210</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E8 211</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E9 212</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E10 213</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E11 214</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E12 215</span><br><span> </span><br><span> /* Group F */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F0 165</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F1 166</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F2 167</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F3 168</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F4 169</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F5 170</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F6 171</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F7 172</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F8 173</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F9 174</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F10 175</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F11 176</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F12 177</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F13 178</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F14 179</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F15 180</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F16 181</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F17 182</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F18 183</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F19 184</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F20 185</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F21 186</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F22 187</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F23 188</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F0 216</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F1 217</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F2 218</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F3 219</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F4 220</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F5 221</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F6 222</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F7 223</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F8 224</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F9 225</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F10 226</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F11 227</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F12 228</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F13 229</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F14 230</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F15 231</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F16 232</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F17 233</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F18 234</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F19 235</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F20 236</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F21 237</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F22 238</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F23 239</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define NUM_GPIO_COM3_PADS (GPP_F23 - GPP_K0 + 1)</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_51 240</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_52 241</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_53 242</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_54 243</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_55 244</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_56 245</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_57 246</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_58 247</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_59 248</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define NUM_GPIO_COM3_PADS (GPIO_RSVD_59 - GPP_K0 + 1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* CPU */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_60 249</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_61 250</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_62 251</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_63 252</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_64 253</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_65 254</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_66 255</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_67 256</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_68 257</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_69 258</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_70 259</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* JTAG */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_71 260</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_72 261</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_73 262</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_74 263</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_75 264</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_76 265</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_77 266</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_78 267</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_79 268</span><br><span> </span><br><span> /* Group I */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_I0 189</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_I1 190</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_I2 191</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_I3 192</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_I4 193</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_I5 194</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_I6 195</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_I7 196</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_I8 197</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_I9 198</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_I10 199</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_I11 200</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_I12 201</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_I13 202</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_I14 203</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I0 269</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I1 270</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I2 271</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I3 272</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I4 273</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I5 274</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I6 275</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I7 276</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I8 277</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I9 278</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I10 279</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I11 280</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I12 281</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I13 282</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I14 283</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_80 284</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_81 285</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_RSVD_82 286</span><br><span> </span><br><span> /* Group J */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_J0 204</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_J1 205</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_J2 206</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_J3 207</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_J4 208</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_J5 209</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_J6 210</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_J7 211</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_J8 212</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_J9 213</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_J10 214</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_J11 215</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J0 287</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J1 288</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J2 289</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J3 290</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J4 291</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J5 292</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J6 293</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J7 294</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J8 295</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J9 296</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J10 297</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J11 298</span><br><span> </span><br><span> #define NUM_GPIO_COM4_PADS (GPP_J11 - GPP_I0 + 1)</span><br><span> </span><br><span> /* Group GPD */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD0 216</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD1 217</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD2 218</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD3 219</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD4 220</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD5 221</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD6 222</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD7 223</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD8 224</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD9 225</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD10 226</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD11 227</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD0 299</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD1 300</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD2 301</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD3 302</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD4 303</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD5 304</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD6 305</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD7 306</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD8 307</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD9 308</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD10 309</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD11 310</span><br><span> </span><br><span> #define NUM_GPIO_COM2_PADS (GPD11 - GPD0 + 1)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define TOTAL_PADS (GPD11 + 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TOTAL_PADS (GPD11 + 1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #endif</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30134">change 30134</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30134"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: Ife7d3090d654b0b88c6911befa08bf6abd4f2ff9 </div>
<div style="display:none"> Gerrit-Change-Number: 30134 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Duncan Laurie <dlaurie@chromium.org> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>