<p>Subrata Banik <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30015">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Subrata Banik: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/intel/icelake_rvp: Fill Icelake U and Y RVP devicetree parameters<br><br>This implementation configures below parameters:<br><br>1. Enable SaGv, isclk.<br>2. Set Pcie rootport enable, Clock source usage and clkreq.<br>3. Configure SATA and LPSS controllers parameters.<br>4. Enable CNVI controller, configure Wifi end device under PCIE RP1.<br>5. Add TPM device support under GSPI1.<br><br>Change-Id: I585e82799eea0bad19ad2c94d6b4b3024f930ed4<br>Signed-off-by: Aamir Bohra <aamir.bohra@intel.com><br>Reviewed-on: https://review.coreboot.org/c/30015<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb<br>M src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb<br>M src/soc/intel/icelake/chip.h<br>3 files changed, 279 insertions(+), 64 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb</span><br><span>index a971332..0d2ea76 100644</span><br><span>--- a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb</span><br><span>@@ -4,28 +4,40 @@</span><br><span> device lapic 0 on end</span><br><span> end</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ # GPE configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ # Note that GPE events called out in ASL code rely on this</span><br><span style="color: hsl(120, 100%, 40%);">+ # route. i.e. If this route changes then the affected GPE</span><br><span style="color: hsl(120, 100%, 40%);">+ # offset bits also need to be changed.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw0" = "GPP_B"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw1" = "GPP_D"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw2" = "GPP_E"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> # FSP configuration</span><br><span style="color: hsl(0, 100%, 40%);">- register "SaGv" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SaGv" = "SaGv_Enabled"</span><br><span> register "SmbusEnable" = "1"</span><br><span> register "ScsEmmcHs400Enabled" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SdCardPowerEnableActiveHigh" = "1"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB3/2 Type A port1</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # USB2 WWAN</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # USB2 Bluetooth</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB2 WWAN</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Bluetooth</span><br><span> register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # Type-C Port1</span><br><span> register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-C Port3</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # Type-C Port4</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" # Type-C Port4</span><br><span> register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" # USB2 Type A port2</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" # USB2 Type A port2</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB2 Type A port1</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # USB2 Type A port2</span><br><span> </span><br><span> register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1</span><br><span> register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3 WLAN</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" # UNUSED</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # UNUSED</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # UNUSED</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WLAN</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable Pch iSCLK</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pch_isclk" = "1"</span><br><span> </span><br><span> # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f</span><br><span> register "gen1_dec" = "0x00fc0801"</span><br><span>@@ -36,6 +48,8 @@</span><br><span> register "PchHdaDspEnable" = "1"</span><br><span> register "PchHdaAudioLinkHda" = "1"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ register "PrmrrSize" = "0x10000000"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> register "PcieRpEnable[0]" = "1"</span><br><span> register "PcieRpEnable[1]" = "1"</span><br><span> register "PcieRpEnable[2]" = "1"</span><br><span>@@ -53,12 +67,22 @@</span><br><span> register "PcieRpEnable[14]" = "1"</span><br><span> register "PcieRpEnable[15]" = "1"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- register "PcieClkSrcUsage[0]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[0]" = "2"</span><br><span> register "PcieClkSrcUsage[1]" = "8"</span><br><span style="color: hsl(0, 100%, 40%);">- register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"</span><br><span style="color: hsl(0, 100%, 40%);">- register "PcieClkSrcUsage[3]" = "13"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[2]" = "0xC"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[3]" = "0x70"</span><br><span> register "PcieClkSrcUsage[4]" = "4"</span><br><span style="color: hsl(0, 100%, 40%);">- register "PcieClkSrcUsage[5]" = "14"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[5]" = "0xE"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[6]" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[7]" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[8]" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[9]" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[10]" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[11]" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[12]" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[13]" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[14]" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[15]" = "0x80"</span><br><span> </span><br><span> register "PcieClkSrcClkReq[0]" = "0"</span><br><span> register "PcieClkSrcClkReq[1]" = "1"</span><br><span>@@ -66,6 +90,69 @@</span><br><span> register "PcieClkSrcClkReq[3]" = "3"</span><br><span> register "PcieClkSrcClkReq[4]" = "4"</span><br><span> register "PcieClkSrcClkReq[5]" = "5"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[6]" = "6"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[7]" = "7"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[8]" = "8"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[9]" = "9"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[10]" = "10"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[11]" = "11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[12]" = "12"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[13]" = "13"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[14]" = "14"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[15]" = "15"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataSalpSupport" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[0]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[1]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[2]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[3]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[4]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[5]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[6]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[7]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsDevSlp[0]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsDevSlp[1]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsDevSlp[2]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsDevSlp[3]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsDevSlp[4]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsDevSlp[5]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsDevSlp[6]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsDevSlp[7]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SerialIoI2cMode" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C0] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C1] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C2] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C3] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C4] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C5] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SerialIoGSpiMode" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexGSPI0] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexGSPI1] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexGSPI2] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SerialIoGSpiCsMode" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexGSPI0] = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexGSPI1] = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexGSPI2] = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SerialIoGSpiCsState" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexGSPI0] = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexGSPI1] = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexGSPI2] = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SerialIoUartMode" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexUART0] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexUART1] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexUART2] = PchSerialIoSkipInit,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span> </span><br><span> # Enable "Intel Speed Shift Technology"</span><br><span> register "speed_shift_enable" = "1"</span><br><span>@@ -74,29 +161,32 @@</span><br><span> register "sdcard_cd_gpio" = "GPP_G5"</span><br><span> </span><br><span> # Enable S0ix</span><br><span style="color: hsl(0, 100%, 40%);">- register "s0ix_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "s0ix_enable" = "0"</span><br><span> </span><br><span> # Intel Common SoC Config</span><br><span> #+-------------------+---------------------------+</span><br><span> #| Field | Value |</span><br><span> #+-------------------+---------------------------+</span><br><span> #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |</span><br><span style="color: hsl(0, 100%, 40%);">- #| I2C3 | Audio |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| GSPI1 | cr50 TPM. Early init is |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| | required to set up a BAR |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| | for TPM communication |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| | before memory is up |</span><br><span> #+-------------------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> register "common_soc_config" = "{</span><br><span> .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,</span><br><span style="color: hsl(0, 100%, 40%);">- .i2c[3] = {</span><br><span style="color: hsl(0, 100%, 40%);">- .speed = I2C_SPEED_STANDARD,</span><br><span style="color: hsl(0, 100%, 40%);">- .rise_time_ns = 104,</span><br><span style="color: hsl(0, 100%, 40%);">- .fall_time_ns = 52,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gspi[1] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed_mhz = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .early_init = 1,</span><br><span> },</span><br><span> }"</span><br><span> </span><br><span> device domain 0 on</span><br><span> device pci 00.0 on end # Host Bridge</span><br><span> device pci 02.0 on end # Integrated Graphics Device</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 04.0 on end # SA Thermal device</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 12.0 on end # Thermal Subsystem</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 04.0 off end # SA Thermal device</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.0 off end # Thermal Subsystem</span><br><span> device pci 12.5 off end # UFS SCS</span><br><span> device pci 12.6 off end # GSPI #2</span><br><span> device pci 14.0 on</span><br><span>@@ -188,6 +278,7 @@</span><br><span> end</span><br><span> end # USB xHCI</span><br><span> device pci 14.1 off end # USB xDCI (OTG)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.2 off end # PMC SRAM</span><br><span> chip drivers/intel/wifi</span><br><span> register "wake" = "GPE0_PME_B0"</span><br><span> device pci 14.3 on end # CNVi wifi</span><br><span>@@ -203,7 +294,7 @@</span><br><span> end</span><br><span> end # I2C 0</span><br><span> device pci 15.1 on end # I2C #1</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 15.2 off end # I2C #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.2 on end # I2C #2</span><br><span> device pci 15.3 on end # I2C #3</span><br><span> device pci 16.0 on end # Management Engine Interface 1</span><br><span> device pci 16.1 off end # Management Engine Interface 2</span><br><span>@@ -211,12 +302,17 @@</span><br><span> device pci 16.3 off end # Management Engine KT Redirection</span><br><span> device pci 16.4 off end # Management Engine Interface 3</span><br><span> device pci 16.5 off end # Management Engine Interface 4</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 17.0 off end # SATA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.0 on end # SATA</span><br><span> device pci 19.0 on end # I2C #4</span><br><span> device pci 19.1 off end # I2C #5</span><br><span> device pci 19.2 on end # UART #2</span><br><span> device pci 1a.0 on end # eMMC</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/intel/wifi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "wake" = "GPE0_PCI_EXP"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # PCI Express Port 1 x4 SLOT1</span><br><span> device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN</span><br><span> device pci 1c.5 off end # PCI Express Port 6</span><br><span> device pci 1c.6 off end # PCI Express Port 7</span><br><span>@@ -232,12 +328,15 @@</span><br><span> device pci 1e.0 on end # UART #0</span><br><span> device pci 1e.1 off end # UART #1</span><br><span> device pci 1e.2 off end # GSPI #0</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1e.3 off end # GSPI #1</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1f.0 on</span><br><span style="color: hsl(0, 100%, 40%);">- chip drivers/pc80/tpm</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 0c31.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.3 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/spi/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "hid" = "ACPI_DT_NAMESPACE_HID"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "compat_string" = ""google,cr50""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"</span><br><span style="color: hsl(120, 100%, 40%);">+ device spi 0 on end</span><br><span> end</span><br><span style="color: hsl(0, 100%, 40%);">- end # LPC Interface</span><br><span style="color: hsl(120, 100%, 40%);">+ end # GSPI #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on end # eSPI Interface</span><br><span> device pci 1f.1 on end # P2SB</span><br><span> device pci 1f.2 on end # Power Management Controller</span><br><span> device pci 1f.3 on end # Intel HDA</span><br><span>diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb</span><br><span>index 787097e..62c7a82 100644</span><br><span>--- a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb</span><br><span>@@ -4,28 +4,40 @@</span><br><span> device lapic 0 on end</span><br><span> end</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ # GPE configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ # Note that GPE events called out in ASL code rely on this</span><br><span style="color: hsl(120, 100%, 40%);">+ # route. i.e. If this route changes then the affected GPE</span><br><span style="color: hsl(120, 100%, 40%);">+ # offset bits also need to be changed.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw0" = "GPP_B"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw1" = "GPP_D"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw2" = "GPP_E"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> # FSP configuration</span><br><span style="color: hsl(0, 100%, 40%);">- register "SaGv" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SaGv" = "SaGv_Disabled"</span><br><span> register "SmbusEnable" = "1"</span><br><span> register "ScsEmmcHs400Enabled" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SdCardPowerEnableActiveHigh" = "1"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB3/2 Type A port1</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB3/2 Type A port2</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # Bluetooth</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB3/2 Type A port2</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth</span><br><span> register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # Type-C Port1</span><br><span> register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-C Port3</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[6]" = "USB2_PORT_EMPTY" # UNUSED</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[7]" = "USB2_PORT_EMPTY" # UNUSED</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[8]" = "USB2_PORT_EMPTY" # USB2 Type A port1</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" # USB2 Type A port2</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # UNUSED</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # UNUSED</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Type A port1</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Type A port2</span><br><span> </span><br><span> register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1</span><br><span> register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3 WLAN</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" # UNUSED</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # UNUSED</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # UNUSED</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WLAN</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable Pch iSCLK</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pch_isclk" = "1"</span><br><span> </span><br><span> # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f</span><br><span> register "gen1_dec" = "0x00fc0801"</span><br><span>@@ -35,8 +47,8 @@</span><br><span> </span><br><span> register "PchHdaDspEnable" = "1"</span><br><span> register "PchHdaAudioLinkHda" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "PchHdaAudioLinkSsp0" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "PchHdaAudioLinkSsp1" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PrmrrSize" = "0x10000000"</span><br><span> </span><br><span> register "PcieRpEnable[0]" = "1"</span><br><span> register "PcieRpEnable[1]" = "1"</span><br><span>@@ -52,13 +64,25 @@</span><br><span> register "PcieRpEnable[11]" = "1"</span><br><span> register "PcieRpEnable[12]" = "1"</span><br><span> register "PcieRpEnable[13]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[14]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[15]" = "1"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[0]" = "0x80"</span><br><span> register "PcieClkSrcUsage[1]" = "8"</span><br><span style="color: hsl(0, 100%, 40%);">- register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"</span><br><span style="color: hsl(0, 100%, 40%);">- register "PcieClkSrcUsage[3]" = "14"</span><br><span style="color: hsl(0, 100%, 40%);">- register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED"</span><br><span style="color: hsl(0, 100%, 40%);">- register "PcieClkSrcUsage[5]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[2]" = "0xC"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[3]" = "0x70"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[4]" = "4"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[5]" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[6]" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[7]" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[8]" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[9]" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[10]" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[11]" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[12]" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[13]" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[14]" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[15]" = "0x80"</span><br><span> </span><br><span> register "PcieClkSrcClkReq[0]" = "0"</span><br><span> register "PcieClkSrcClkReq[1]" = "1"</span><br><span>@@ -66,6 +90,69 @@</span><br><span> register "PcieClkSrcClkReq[3]" = "3"</span><br><span> register "PcieClkSrcClkReq[4]" = "4"</span><br><span> register "PcieClkSrcClkReq[5]" = "5"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[6]" = "6"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[7]" = "7"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[8]" = "8"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[9]" = "9"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[10]" = "10"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[11]" = "11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[12]" = "12"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[13]" = "13"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[14]" = "14"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[15]" = "15"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataSalpSupport" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[0]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[1]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[2]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[3]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[4]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[5]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[6]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[7]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsDevSlp[0]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsDevSlp[1]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsDevSlp[2]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsDevSlp[3]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsDevSlp[4]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsDevSlp[5]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsDevSlp[6]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsDevSlp[7]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SerialIoI2cMode" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C0] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C1] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C2] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C3] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C4] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C5] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SerialIoGSpiMode" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexGSPI0] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexGSPI1] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexGSPI2] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SerialIoGSpiCsMode" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexGSPI0] = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexGSPI1] = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexGSPI2] = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SerialIoGSpiCsState" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexGSPI0] = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexGSPI1] = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexGSPI2] = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SerialIoUartMode" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexUART0] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexUART1] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexUART2] = PchSerialIoSkipInit,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span> </span><br><span> # Enable "Intel Speed Shift Technology"</span><br><span> register "speed_shift_enable" = "1"</span><br><span>@@ -74,13 +161,32 @@</span><br><span> register "sdcard_cd_gpio" = "GPP_G5"</span><br><span> </span><br><span> # Enable S0ix</span><br><span style="color: hsl(0, 100%, 40%);">- register "s0ix_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "s0ix_enable" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Intel Common SoC Config</span><br><span style="color: hsl(120, 100%, 40%);">+ #+-------------------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Field | Value |</span><br><span style="color: hsl(120, 100%, 40%);">+ #+-------------------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| GSPI1 | cr50 TPM. Early init is |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| | required to set up a BAR |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| | for TPM communication |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| | before memory is up |</span><br><span style="color: hsl(120, 100%, 40%);">+ #+-------------------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "common_soc_config" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gspi[1] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed_mhz = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .early_init = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span> </span><br><span> device domain 0 on</span><br><span> device pci 00.0 on end # Host Bridge</span><br><span> device pci 02.0 on end # Integrated Graphics Device</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 04.0 on end # SA Thermal device</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 12.0 on end # Thermal Subsystem</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 04.0 off end # SA Thermal device</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.0 off end # Thermal Subsystem</span><br><span> device pci 12.5 off end # UFS SCS</span><br><span> device pci 12.6 off end # GSPI #2</span><br><span> device pci 14.0 on</span><br><span>@@ -172,6 +278,7 @@</span><br><span> end</span><br><span> end # USB xHCI</span><br><span> device pci 14.1 off end # USB xDCI (OTG)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.2 off end # PMC SRAM</span><br><span> chip drivers/intel/wifi</span><br><span> register "wake" = "GPE0_PME_B0"</span><br><span> device pci 14.3 on end # CNVi wifi</span><br><span>@@ -187,20 +294,25 @@</span><br><span> end</span><br><span> end # I2C 0</span><br><span> device pci 15.1 on end # I2C #1</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 15.2 off end # I2C #2</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 15.3 on end # I2C #3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.2 on end # I2C #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.3 on end # I2C #3</span><br><span> device pci 16.0 on end # Management Engine Interface 1</span><br><span> device pci 16.1 off end # Management Engine Interface 2</span><br><span> device pci 16.2 off end # Management Engine IDE-R</span><br><span> device pci 16.3 off end # Management Engine KT Redirection</span><br><span> device pci 16.4 off end # Management Engine Interface 3</span><br><span> device pci 16.5 off end # Management Engine Interface 4</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 17.0 off end # SATA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.0 on end # SATA</span><br><span> device pci 19.0 on end # I2C #4</span><br><span> device pci 19.1 off end # I2C #5</span><br><span> device pci 19.2 on end # UART #2</span><br><span> device pci 1a.0 on end # eMMC</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/intel/wifi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "wake" = "GPE0_PCI_EXP"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # PCI Express Port 1 x4 SLOT1</span><br><span> device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN</span><br><span> device pci 1c.5 off end # PCI Express Port 6</span><br><span> device pci 1c.6 off end # PCI Express Port 7</span><br><span>@@ -216,12 +328,15 @@</span><br><span> device pci 1e.0 on end # UART #0</span><br><span> device pci 1e.1 off end # UART #1</span><br><span> device pci 1e.2 off end # GSPI #0</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1e.3 off end # GSPI #1</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1f.0 on</span><br><span style="color: hsl(0, 100%, 40%);">- chip drivers/pc80/tpm</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 0c31.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.3 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/spi/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "hid" = "ACPI_DT_NAMESPACE_HID"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "compat_string" = ""google,cr50""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"</span><br><span style="color: hsl(120, 100%, 40%);">+ device spi 0 on end</span><br><span> end</span><br><span style="color: hsl(0, 100%, 40%);">- end # LPC Interface</span><br><span style="color: hsl(120, 100%, 40%);">+ end # GSPI #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on end # eSPI Interface</span><br><span> device pci 1f.1 on end # P2SB</span><br><span> device pci 1f.2 on end # Power Management Controller</span><br><span> device pci 1f.3 on end # Intel HDA</span><br><span>diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h</span><br><span>index c8653b2..3e2b78a 100644</span><br><span>--- a/src/soc/intel/icelake/chip.h</span><br><span>+++ b/src/soc/intel/icelake/chip.h</span><br><span>@@ -115,6 +115,7 @@</span><br><span> uint16_t usb3_wake_enable_bitmap;</span><br><span> </span><br><span> /* SATA related */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t SataEnable;</span><br><span> uint8_t SataMode;</span><br><span> uint8_t SataSalpSupport;</span><br><span> uint8_t SataPortsEnable[8];</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30015">change 30015</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30015"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I585e82799eea0bad19ad2c94d6b4b3024f930ed4 </div>
<div style="display:none"> Gerrit-Change-Number: 30015 </div>
<div style="display:none"> Gerrit-PatchSet: 2 </div>
<div style="display:none"> Gerrit-Owner: Aamir Bohra <aamir.bohra@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Aamir Bohra <aamir.bohra@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> </div>
<div style="display:none"> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Shelley Chen <shchen@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-MessageType: merged </div>