<p>Duncan Laurie has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30133">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Add GPIO group pad base for ACPI<br><br>The GPIO drivers in Windows and Linux for the Cannonlake CPU<br>have a sparse GPIO map and do not allocate pins contiguously.<br>Each GPIO group is allocated as 32 pads regardless of whether<br>the hardware actually has that many in the group.<br><br>It appears this originated with a bug in Windows/UEFI and was<br>carried over to Linux in order to work with existing firmware:<br>https://lore.kernel.org/patchwork/patch/855244/<br><br>In order to support using ACPI GPIOs it is necessary for coreboot<br>to be compatible with this implementation. The GPIO groups that<br>are usable by the OS are declared with a pad base which is then<br>used to compute the number for ACPI GPIOs.<br><br>BUG=b:120686247<br>TEST=tested with write protect GPIO on sarien board. Before this<br>change the ACPI pin number was 220 which did not correspond to the<br>pin number in Linux. After this change the ACPI number is 303,<br>which maps to the correct GPIO in Linux. Now the GPIO value reported<br>by the kernel changes when the WP pin is toggled in hardware.<br><br>Change-Id: I4f1a9e118d7e48f2445ccbb62a12a22e9a832c51<br>Signed-off-by: Duncan Laurie <dlaurie@google.com><br>---<br>M src/soc/intel/cannonlake/gpio.c<br>1 file changed, 28 insertions(+), 13 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/30133/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c</span><br><span>index 2705bcf..701eb0b 100644</span><br><span>--- a/src/soc/intel/cannonlake/gpio.c</span><br><span>+++ b/src/soc/intel/cannonlake/gpio.c</span><br><span>@@ -32,34 +32,49 @@</span><br><span> { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },</span><br><span> };</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * The GPIO driver for Cannonlake on Windows/Linux expects 32 GPIOs per pad</span><br><span style="color: hsl(120, 100%, 40%);">+ * group, regardless of whether or not there is a physical pad for each</span><br><span style="color: hsl(120, 100%, 40%);">+ * exposed GPIO number.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This results in the OS having a sparse GPIO map, and devices that need</span><br><span style="color: hsl(120, 100%, 40%);">+ * to export an ACPI GPIO must use the OS expected number.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Not all pins are usable as GPIO and those groups do not have a pad base.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This layout matches the Linux kernel pinctrl map for CNL-LP at:</span><br><span style="color: hsl(120, 100%, 40%);">+ * linux/drivers/pinctrl/intel/pinctrl-cannonlake.c</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span> static const struct pad_group cnl_community0_groups[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_A0, GPP_A0, GPIO_RSVD_0), /* GPP_A */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_A0, GPP_B0, GPIO_RSVD_2), /* GPP_B */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_A0, GPP_G0, GPP_G7), /* GPP_G */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_A0, GPIO_RSVD_3, GPIO_RSVD_11), /* SPI */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP_BASE(GPP_A0, GPP_A0, GPIO_RSVD_0, 0), /* GPP_A */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP_BASE(GPP_A0, GPP_B0, GPIO_RSVD_2, 32), /* GPP_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP_BASE(GPP_A0, GPP_G0, GPP_G7, 64), /* GPP_G */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_A0, GPIO_RSVD_3, GPIO_RSVD_11), /* SPI */</span><br><span> };</span><br><span> </span><br><span> static const struct pad_group cnl_community1_groups[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_D0, GPP_D0, GPIO_RSVD_12), /* GPP_D */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_D0, GPP_F0, GPP_F23), /* GPP_F */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_D0, GPP_H0, GPP_H23), /* GPP_H */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_D0, GPIO_RSVD_13, GPIO_RSVD_52), /* VGPIO */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP_BASE(GPP_D0, GPP_D0, GPIO_RSVD_12, 96), /* GPP_D */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP_BASE(GPP_D0, GPP_F0, GPP_F23, 128), /* GPP_F */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP_BASE(GPP_D0, GPP_H0, GPP_H23, 160), /* GPP_H */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP_BASE(GPP_D0, GPIO_RSVD_13, GPIO_RSVD_52, 192),/* VGPIO */</span><br><span> };</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* This community is not visible to the OS */</span><br><span> static const struct pad_group cnl_community2_groups[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPD0, GPD0, GPD11), /* GPD */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPD0, GPD0, GPD11), /* GPD */</span><br><span> };</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* This community is not visible to the OS */</span><br><span> static const struct pad_group cnl_community3_groups[] = {</span><br><span> INTEL_GPP(HDA_BCLK, HDA_BCLK, SSP1_TXD), /* AZA */</span><br><span> INTEL_GPP(HDA_BCLK, GPIO_RSVD_68, GPIO_RSVD_78), /* CPU */</span><br><span> };</span><br><span> </span><br><span> static const struct pad_group cnl_community4_groups[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP_C */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_C0, GPP_E0, GPP_E23), /* GPP_E */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_C0, GPIO_RSVD_53, GPIO_RSVD_61), /* JTAG */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_C0, GPIO_RSVD_62, GPIO_RSVD_67), /* HVMOS */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 256), /* GPP_C */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E23, 288), /* GPP_E */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_C0, GPIO_RSVD_53, GPIO_RSVD_61), /* JTAG */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_C0, GPIO_RSVD_62, GPIO_RSVD_67), /* HVMOS */</span><br><span> };</span><br><span> </span><br><span> static const struct pad_community cnl_communities[] = {</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30133">change 30133</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I4f1a9e118d7e48f2445ccbb62a12a22e9a832c51 </div>
<div style="display:none"> Gerrit-Change-Number: 30133 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Duncan Laurie <dlaurie@chromium.org> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>