<p>Duncan Laurie has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30112">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Fix GPIO reporting<br><br>The kernel GPIO driver only expects GPIO communities 0, 1, and 4 to<br>be exported in the _CRS and it will not work correctly if the other<br>communities are exported.<br><br>Additionally one of the pin offset values was incorrect in GPIO<br>community 1.  This doesn't have any specific failure mode but it was<br>found when auditing the GPIO code.<br><br>BUG=b:120686247<br>TEST=check /sys/kernel/debug/pinctrl/INT34BB:00/pins to ensure that<br>pins >= 198 are not reading all zeros for the pin config registers.<br><br>Change-Id: Ie1a2f3b9f9f4b24a9fc57e468dee50e99753912f<br>Signed-off-by: Duncan Laurie <dlaurie@google.com><br>---<br>M src/soc/intel/cannonlake/acpi/gpio.asl<br>M src/soc/intel/cannonlake/gpio.c<br>2 files changed, 1 insertion(+), 16 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/30112/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/acpi/gpio.asl b/src/soc/intel/cannonlake/acpi/gpio.asl</span><br><span>index 8a990b3..bf4fc5e 100644</span><br><span>--- a/src/soc/intel/cannonlake/acpi/gpio.asl</span><br><span>+++ b/src/soc/intel/cannonlake/acpi/gpio.asl</span><br><span>@@ -28,8 +28,6 @@</span><br><span>    {</span><br><span>            Memory32Fixed (ReadWrite, 0, 0, COM0)</span><br><span>                Memory32Fixed (ReadWrite, 0, 0, COM1)</span><br><span style="color: hsl(0, 100%, 40%);">-           Memory32Fixed (ReadWrite, 0, 0, COM2)</span><br><span style="color: hsl(0, 100%, 40%);">-           Memory32Fixed (ReadWrite, 0, 0, COM3)</span><br><span>                Memory32Fixed (ReadWrite, 0, 0, COM4)</span><br><span>                Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)</span><br><span>                       { GPIO_IRQ14 }</span><br><span>@@ -49,19 +47,6 @@</span><br><span>          Store (^^PCRB (PID_GPIOCOM1), BAS1)</span><br><span>          Store (GPIO_BASE_SIZE, LEN1)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-                /* GPIO Community 2 */</span><br><span style="color: hsl(0, 100%, 40%);">-          CreateDWordField (^RBUF, ^COM2._BAS, BAS2)</span><br><span style="color: hsl(0, 100%, 40%);">-              CreateDWordField (^RBUF, ^COM2._LEN, LEN2)</span><br><span style="color: hsl(0, 100%, 40%);">-              Store (^^PCRB (PID_GPIOCOM2), BAS2)</span><br><span style="color: hsl(0, 100%, 40%);">-             Store (GPIO_BASE_SIZE, LEN2)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-            /* GPIO Community 3 */</span><br><span style="color: hsl(0, 100%, 40%);">-          CreateDWordField (^RBUF, ^COM3._BAS, BAS3)</span><br><span style="color: hsl(0, 100%, 40%);">-              CreateDWordField (^RBUF, ^COM3._LEN, LEN3)</span><br><span style="color: hsl(0, 100%, 40%);">-              Store (^^PCRB (PID_GPIOCOM3), BAS3)</span><br><span style="color: hsl(0, 100%, 40%);">-             Store (GPIO_BASE_SIZE, LEN3)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span>                 /* GPIO Community 4 */</span><br><span>               CreateDWordField (^RBUF, ^COM4._BAS, BAS4)</span><br><span>           CreateDWordField (^RBUF, ^COM4._LEN, LEN4)</span><br><span>diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c</span><br><span>index 0befba0..2705bcf 100644</span><br><span>--- a/src/soc/intel/cannonlake/gpio.c</span><br><span>+++ b/src/soc/intel/cannonlake/gpio.c</span><br><span>@@ -43,7 +43,7 @@</span><br><span>      INTEL_GPP(GPP_D0, GPP_D0, GPIO_RSVD_12),        /* GPP_D */</span><br><span>  INTEL_GPP(GPP_D0, GPP_F0, GPP_F23),             /* GPP_F */</span><br><span>  INTEL_GPP(GPP_D0, GPP_H0, GPP_H23),             /* GPP_H */</span><br><span style="color: hsl(0, 100%, 40%);">-     INTEL_GPP(GPP_D0, GPIO_RSVD_12, GPIO_RSVD_52),  /* VGPIO */</span><br><span style="color: hsl(120, 100%, 40%);">+   INTEL_GPP(GPP_D0, GPIO_RSVD_13, GPIO_RSVD_52),  /* VGPIO */</span><br><span> };</span><br><span> </span><br><span> static const struct pad_group cnl_community2_groups[] = {</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30112">change 30112</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30112"/><meta itemprop="name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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: Ie1a2f3b9f9f4b24a9fc57e468dee50e99753912f </div>
<div style="display:none"> Gerrit-Change-Number: 30112 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Duncan Laurie <dlaurie@chromium.org> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>