<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30100">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/sarien: Enable LAN clock source usage<br><br>FSP defined a special clock source usage 0x70 for PCH LAN device, update<br>that to google sarien platform.<br><br>BUG=b:120003760<br>TEST=Boot up into OS, ethernet able to be listed in ifconfig.<br><br>Change-Id: I9f945be4f0ce15470ab53f44e60143f3fd0fddf8<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/mainboard/google/sarien/variants/arcada/devicetree.cb<br>M src/mainboard/google/sarien/variants/sarien/devicetree.cb<br>2 files changed, 2 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/30100/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb</span><br><span>index f487979..91bda9c 100644</span><br><span>--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb</span><br><span>+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb</span><br><span>@@ -76,7 +76,7 @@</span><br><span> </span><br><span>  # PCIe port 9 for LAN</span><br><span>        register "PcieRpEnable[8]" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">-    register "PcieClkSrcUsage[0]" = "8"</span><br><span style="color: hsl(120, 100%, 40%);">+       register "PcieClkSrcUsage[0]" = "PCIE_CLK_LAN"</span><br><span>   register "PcieClkSrcClkReq[0]" = "0"</span><br><span> </span><br><span>         # PCIe port 10 for M.2 2230 WLAN</span><br><span>diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb</span><br><span>index 5004abf..a960252 100644</span><br><span>--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb</span><br><span>+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb</span><br><span>@@ -81,7 +81,7 @@</span><br><span> </span><br><span>    # PCIe port 9 for LAN</span><br><span>        register "PcieRpEnable[8]" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">-    register "PcieClkSrcUsage[3]" = "8"</span><br><span style="color: hsl(120, 100%, 40%);">+       register "PcieClkSrcUsage[3]" = "PCIE_CLK_LAN"</span><br><span>   register "PcieClkSrcClkReq[3]" = "3"</span><br><span> </span><br><span>         # PCIe port 10 for M.2 2230 WLAN</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30100">change 30100</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30100"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I9f945be4f0ce15470ab53f44e60143f3fd0fddf8 </div>
<div style="display:none"> Gerrit-Change-Number: 30100 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>