<p>Tristan Corrick has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30077">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/lynxpoint: Handle H81 only having 6 PCIe root ports<br><br>The H81 chipset is the only non-LP Lynx Point chipset with 6 PCIe root<br>ports, all others have 8 [1]. The existing PCIe code assumed that all<br>non-LP chipsets had 8 root ports, which meant that port 6 would not be<br>considered the last root port on H81, so `root_port_commit_config()`<br>would not run. Ultimately, while PCIe still worked on H81, all the root<br>ports would remain enabled, even if disabled in the devicetree.<br><br>Also, remove `PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_{MIN,MAX}`, as they<br>are unused, and the MAX constant is incorrect.<br><br>Interestingly, this fixes an issue where GRUB is unable to halt the<br>system.<br><br>Tested on an ASRock H81M-HDS. The root ports disabled in the devicetree<br>do indeed end up disabled.<br><br>[1] Intel® 8 Series/C220 Series Chipset Family Platform Controller Hub<br> (PCH) Datasheet, revision 003, document number 328904.<br><br>Change-Id: If3ce217e8a4f4ea4e111e4525b03dbbfc63f92b0<br>Signed-off-by: Tristan Corrick <tristan@corrick.kiwi><br>---<br>M src/include/device/pci_ids.h<br>M src/mainboard/asrock/h81m-hds/devicetree.cb<br>M src/southbridge/intel/lynxpoint/pch.c<br>M src/southbridge/intel/lynxpoint/pch.h<br>M src/southbridge/intel/lynxpoint/pcie.c<br>5 files changed, 38 insertions(+), 15 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/30077/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h</span><br><span>index b9c9152..751cca0 100644</span><br><span>--- a/src/include/device/pci_ids.h</span><br><span>+++ b/src/include/device/pci_ids.h</span><br><span>@@ -2661,11 +2661,26 @@</span><br><span> #define PCI_DEVICE_ID_INTEL_PCIE_PB 0x3597</span><br><span> #define PCI_DEVICE_ID_INTEL_PCIE_PC 0x3599</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Intel Lynx Point Device IDS */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_MIN 0x8c41</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_MAX 0x8c4f</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Intel LPC device ids */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_LPT_MOBILE_SAMPLE 0x8c41</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_LPT_DESKTOP_SAMPLE 0x8c42</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_LPT_Z87 0x8c44</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_LPT_Z85 0x8c46</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_LPT_HM86 0x8c49</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_LPT_H87 0x8c4a</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_LPT_HM87 0x8c4b</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_LPT_Q85 0x8c4c</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_LPT_Q87 0x8c4e</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_LPT_QM87 0x8c4f</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_LPT_B85 0x8c50</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_LPT_C222 0x8c52</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_LPT_C224 0x8c54</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_LPT_C226 0x8c56</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_LPT_H81 0x8c5c</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_LPT_LP_SAMPLE 0x9c41</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_LPT_LP_PREMIUM 0x9c43</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_LPT_LP_MAINSTREAM 0x9c45</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_LPT_LP_VALUE 0x9c47</span><br><span> #define PCI_DEVICE_ID_INTEL_SPT_LP_SAMPLE 0x9d41</span><br><span> #define PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE 0x9d43</span><br><span> #define PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM 0x9d48</span><br><span>diff --git a/src/mainboard/asrock/h81m-hds/devicetree.cb b/src/mainboard/asrock/h81m-hds/devicetree.cb</span><br><span>index 32b5978..58a319d 100644</span><br><span>--- a/src/mainboard/asrock/h81m-hds/devicetree.cb</span><br><span>+++ b/src/mainboard/asrock/h81m-hds/devicetree.cb</span><br><span>@@ -102,8 +102,6 @@</span><br><span> device pci 1c.5 on # PCIe 1x slot</span><br><span> subsystemid 0x1849 0x8c1a</span><br><span> end</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1c.6 off end # PCIe port #7</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1c.7 off end # PCIe port #8</span><br><span> device pci 1d.0 on # EHCI controller #1</span><br><span> subsystemid 0x1849 0x8c26</span><br><span> end</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c</span><br><span>index cb01de7..0821a17 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/pch.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/pch.c</span><br><span>@@ -42,6 +42,16 @@</span><br><span> return pch_revision_id;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+int pch_silicon_id(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ static int pch_id = -1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pch_id < 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_id = pci_read_config16(pch_get_lpc_device(), PCI_DEVICE_ID);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return pch_id;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> int pch_silicon_type(void)</span><br><span> {</span><br><span> static int pch_type = -1;</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h</span><br><span>index a28d703..ee041d9 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/pch.h</span><br><span>+++ b/src/southbridge/intel/lynxpoint/pch.h</span><br><span>@@ -141,6 +141,7 @@</span><br><span> #if !defined(__ASSEMBLER__)</span><br><span> void pch_config_rcba(const struct rcba_config_instruction *rcba_config);</span><br><span> int pch_silicon_revision(void);</span><br><span style="color: hsl(120, 100%, 40%);">+int pch_silicon_id(void);</span><br><span> int pch_silicon_type(void);</span><br><span> int pch_is_lp(void);</span><br><span> u16 get_pmbase(void);</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c</span><br><span>index a7966f1..ca76aae 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/pcie.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/pcie.c</span><br><span>@@ -23,10 +23,7 @@</span><br><span> #include "pch.h"</span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* LynxPoint-LP has 6 root ports while non-LP has 8. */</span><br><span> #define MAX_NUM_ROOT_PORTS 8</span><br><span style="color: hsl(0, 100%, 40%);">-#define H_NUM_ROOT_PORTS MAX_NUM_ROOT_PORTS</span><br><span style="color: hsl(0, 100%, 40%);">-#define LP_NUM_ROOT_PORTS (MAX_NUM_ROOT_PORTS - 2)</span><br><span> </span><br><span> struct root_port_config {</span><br><span> /* RPFN is a write-once register so keep a copy until it is written */</span><br><span>@@ -49,10 +46,10 @@</span><br><span> </span><br><span> static inline int max_root_ports(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- if (pch_is_lp())</span><br><span style="color: hsl(0, 100%, 40%);">- return LP_NUM_ROOT_PORTS;</span><br><span style="color: hsl(0, 100%, 40%);">- else</span><br><span style="color: hsl(0, 100%, 40%);">- return H_NUM_ROOT_PORTS;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pch_is_lp() || pch_silicon_id() == PCI_DEVICE_ID_INTEL_LPT_H81)</span><br><span style="color: hsl(120, 100%, 40%);">+ return 6;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return 8;</span><br><span> }</span><br><span> </span><br><span> static inline int root_port_is_first(struct device *dev)</span><br><span>@@ -208,8 +205,10 @@</span><br><span> pci_update_config8(dev, 0xe1, 0x7f, 0x80);</span><br><span> }</span><br><span> if (rp == 5 && !rpc.ports[5]->enabled &&</span><br><span style="color: hsl(0, 100%, 40%);">- !rpc.ports[6]->enabled &&</span><br><span style="color: hsl(0, 100%, 40%);">- !rpc.ports[7]->enabled) {</span><br><span style="color: hsl(120, 100%, 40%);">+ (rpc.ports[6] == NULL ||</span><br><span style="color: hsl(120, 100%, 40%);">+ !rpc.ports[6]->enabled) &&</span><br><span style="color: hsl(120, 100%, 40%);">+ (rpc.ports[7] == NULL ||</span><br><span style="color: hsl(120, 100%, 40%);">+ !rpc.ports[7]->enabled)) {</span><br><span> pci_update_config8(dev, 0xe2, ~1, 1);</span><br><span> pci_update_config8(dev, 0xe1, 0x7f, 0x80);</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30077">change 30077</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30077"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: If3ce217e8a4f4ea4e111e4525b03dbbfc63f92b0 </div>
<div style="display:none"> Gerrit-Change-Number: 30077 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tristan Corrick <tristan@corrick.kiwi> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>