<p>Bob Moragues has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30094">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">zoombini: remove support for deprecated zoombini board<br><br>Change-Id: Iab2737940f07afb4f5a29ff50e6cb2a22027c51b<br>Signed-off-by: Bob Moragues <moragues@chromium.org><br>---<br>D src/mainboard/google/zoombini/Kconfig<br>D src/mainboard/google/zoombini/Kconfig.name<br>D src/mainboard/google/zoombini/Makefile.inc<br>D src/mainboard/google/zoombini/acpi_tables.c<br>D src/mainboard/google/zoombini/board_info.txt<br>D src/mainboard/google/zoombini/bootblock.c<br>D src/mainboard/google/zoombini/chromeos.c<br>D src/mainboard/google/zoombini/chromeos.fmd<br>D src/mainboard/google/zoombini/dsdt.asl<br>D src/mainboard/google/zoombini/ec.c<br>D src/mainboard/google/zoombini/mainboard.c<br>D src/mainboard/google/zoombini/memory.c<br>D src/mainboard/google/zoombini/ramstage.c<br>D src/mainboard/google/zoombini/romstage.c<br>D src/mainboard/google/zoombini/smihandler.c<br>D src/mainboard/google/zoombini/spd/Hynix_H9HCNNN8KUMLHR_1GB.spd.hex<br>D src/mainboard/google/zoombini/spd/Hynix_H9HCNNNCPUMLHR_4GB.spd.hex<br>D src/mainboard/google/zoombini/spd/Makefile.inc<br>D src/mainboard/google/zoombini/spd/Micron_MT53B1024M32D4_4GB.spd.hex<br>D src/mainboard/google/zoombini/spd/Micron_MT53B512M32D2_2GB.spd.hex<br>D src/mainboard/google/zoombini/spd/Samsung_K4F6E3S4HM_2GB.spd.hex<br>D src/mainboard/google/zoombini/spd/Samsung_K4F8E304HB_1GB.spd.hex<br>D src/mainboard/google/zoombini/variants/baseboard/Makefile.inc<br>D src/mainboard/google/zoombini/variants/baseboard/devicetree.cb<br>D src/mainboard/google/zoombini/variants/baseboard/gpio.c<br>D src/mainboard/google/zoombini/variants/baseboard/include/baseboard/acpi/dptf.asl<br>D src/mainboard/google/zoombini/variants/baseboard/include/baseboard/ec.h<br>D src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h<br>D src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h<br>D src/mainboard/google/zoombini/variants/baseboard/nhlt.c<br>D src/mainboard/google/zoombini/variants/meowth/Makefile.inc<br>D src/mainboard/google/zoombini/variants/meowth/devicetree.cb<br>D src/mainboard/google/zoombini/variants/meowth/gpio.c<br>D src/mainboard/google/zoombini/variants/meowth/include/variant/acpi/dptf.asl<br>D src/mainboard/google/zoombini/variants/meowth/include/variant/ec.h<br>D src/mainboard/google/zoombini/variants/meowth/include/variant/gpio.h<br>D src/mainboard/google/zoombini/variants/meowth/memory.c<br>D src/mainboard/google/zoombini/variants/zoombini/Makefile.inc<br>D src/mainboard/google/zoombini/variants/zoombini/include/variant/acpi/dptf.asl<br>D src/mainboard/google/zoombini/variants/zoombini/include/variant/ec.h<br>D src/mainboard/google/zoombini/variants/zoombini/include/variant/gpio.h<br>M util/release/genrelnotes<br>42 files changed, 0 insertions(+), 2,352 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/30094/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/zoombini/Kconfig b/src/mainboard/google/zoombini/Kconfig</span><br><span>deleted file mode 100644</span><br><span>index 249b028..0000000</span><br><span>--- a/src/mainboard/google/zoombini/Kconfig</span><br><span>+++ /dev/null</span><br><span>@@ -1,115 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config BOARD_GOOGLE_BASEBOARD_ZOOMBINI</span><br><span style="color: hsl(0, 100%, 40%);">- def_bool n</span><br><span style="color: hsl(0, 100%, 40%);">- select BOARD_ROMSIZE_KB_16384</span><br><span style="color: hsl(0, 100%, 40%);">- select DRIVERS_I2C_GENERIC</span><br><span style="color: hsl(0, 100%, 40%);">- select DRIVERS_I2C_HID</span><br><span style="color: hsl(0, 100%, 40%);">- select DRIVERS_I2C_MAX98373</span><br><span style="color: hsl(0, 100%, 40%);">- select DRIVERS_SPI_ACPI</span><br><span style="color: hsl(0, 100%, 40%);">- select EC_GOOGLE_CHROMEEC</span><br><span style="color: hsl(0, 100%, 40%);">- select EC_GOOGLE_CHROMEEC_BOARDID</span><br><span style="color: hsl(0, 100%, 40%);">- select EC_GOOGLE_CHROMEEC_LPC</span><br><span style="color: hsl(0, 100%, 40%);">- select HAVE_ACPI_RESUME</span><br><span style="color: hsl(0, 100%, 40%);">- select HAVE_ACPI_TABLES</span><br><span style="color: hsl(0, 100%, 40%);">- select MAINBOARD_HAS_CHROMEOS</span><br><span style="color: hsl(0, 100%, 40%);">- select SOC_INTEL_CANNONLAKE</span><br><span style="color: hsl(0, 100%, 40%);">- select SOC_INTEL_CANNONLAKE_MEMCFG_INIT</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-if BOARD_GOOGLE_BASEBOARD_ZOOMBINI</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config BASEBOARD_ZOOMBINI_LAPTOP</span><br><span style="color: hsl(0, 100%, 40%);">- def_bool n</span><br><span style="color: hsl(0, 100%, 40%);">- select SYSTEM_TYPE_LAPTOP</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config DEVICETREE</span><br><span style="color: hsl(0, 100%, 40%);">- string</span><br><span style="color: hsl(0, 100%, 40%);">- default "variants/meowth/devicetree.cb" if BOARD_GOOGLE_MEOWTH</span><br><span style="color: hsl(0, 100%, 40%);">- default "variants/baseboard/devicetree.cb"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config DIMM_SPD_SIZE</span><br><span style="color: hsl(0, 100%, 40%);">- int</span><br><span style="color: hsl(0, 100%, 40%);">- default 512</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config DRIVER_TPM_I2C_BUS</span><br><span style="color: hsl(0, 100%, 40%);">- depends on ZOOMBINI_USE_I2C_TPM</span><br><span style="color: hsl(0, 100%, 40%);">- default 0x1</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config DRIVER_TPM_I2C_ADDR</span><br><span style="color: hsl(0, 100%, 40%);">- depends on ZOOMBINI_USE_I2C_TPM</span><br><span style="color: hsl(0, 100%, 40%);">- default 0x50</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config DRIVER_TPM_SPI_BUS</span><br><span style="color: hsl(0, 100%, 40%);">- depends on ZOOMBINI_USE_SPI_TPM</span><br><span style="color: hsl(0, 100%, 40%);">- default 0x1</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config GBB_HWID</span><br><span style="color: hsl(0, 100%, 40%);">- string</span><br><span style="color: hsl(0, 100%, 40%);">- depends on CHROMEOS</span><br><span style="color: hsl(0, 100%, 40%);">- default "MEOWTH TEST 5868" if BOARD_GOOGLE_MEOWTH</span><br><span style="color: hsl(0, 100%, 40%);">- default "ZOOMBINI TEST 5722" if BOARD_GOOGLE_ZOOMBINI</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config MAINBOARD_DIR</span><br><span style="color: hsl(0, 100%, 40%);">- string</span><br><span style="color: hsl(0, 100%, 40%);">- default "google/zoombini"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config MAINBOARD_FAMILY</span><br><span style="color: hsl(0, 100%, 40%);">- string</span><br><span style="color: hsl(0, 100%, 40%);">- default "Google_Meowth" if BOARD_GOOGLE_MEOWTH</span><br><span style="color: hsl(0, 100%, 40%);">- default "Google_Zoombini" if BOARD_GOOGLE_ZOOMBINI</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config MAINBOARD_PART_NUMBER</span><br><span style="color: hsl(0, 100%, 40%);">- string</span><br><span style="color: hsl(0, 100%, 40%);">- default "Meowth" if BOARD_GOOGLE_MEOWTH</span><br><span style="color: hsl(0, 100%, 40%);">- default "Zoombini" if BOARD_GOOGLE_ZOOMBINI</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config MAINBOARD_VENDOR</span><br><span style="color: hsl(0, 100%, 40%);">- string</span><br><span style="color: hsl(0, 100%, 40%);">- default "Google"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config INCLUDE_SND_MAX98357_DA7219_NHLT</span><br><span style="color: hsl(0, 100%, 40%);">- bool "Include blobs for audio with MAX98357_DA7219"</span><br><span style="color: hsl(0, 100%, 40%);">- select NHLT_DMIC_4CH_16B</span><br><span style="color: hsl(0, 100%, 40%);">- select NHLT_DMIC_2CH_16B</span><br><span style="color: hsl(0, 100%, 40%);">- select NHLT_DA7219</span><br><span style="color: hsl(0, 100%, 40%);">- select NHLT_MAX98357</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config INCLUDE_SND_MAX98373_NHLT</span><br><span style="color: hsl(0, 100%, 40%);">- bool "Include blobs for audio with MAX98373"</span><br><span style="color: hsl(0, 100%, 40%);">- select NHLT_DMIC_4CH_16B</span><br><span style="color: hsl(0, 100%, 40%);">- select NHLT_DMIC_2CH_16B</span><br><span style="color: hsl(0, 100%, 40%);">- select NHLT_MAX98373</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config MAX_CPUS</span><br><span style="color: hsl(0, 100%, 40%);">- int</span><br><span style="color: hsl(0, 100%, 40%);">- default 4</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config VARIANT_DIR</span><br><span style="color: hsl(0, 100%, 40%);">- string</span><br><span style="color: hsl(0, 100%, 40%);">- default "meowth" if BOARD_GOOGLE_MEOWTH</span><br><span style="color: hsl(0, 100%, 40%);">- default "zoombini" if BOARD_GOOGLE_ZOOMBINI</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config VBOOT</span><br><span style="color: hsl(0, 100%, 40%);">- select EC_GOOGLE_CHROMEEC_SWITCHES</span><br><span style="color: hsl(0, 100%, 40%);">- select HAS_RECOVERY_MRC_CACHE</span><br><span style="color: hsl(0, 100%, 40%);">- select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN</span><br><span style="color: hsl(0, 100%, 40%);">- select VBOOT_LID_SWITCH if BASEBOARD_ZOOMBINI_LAPTOP</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-# Select this option to enable use of cr50 I2C TPM on zoombini.</span><br><span style="color: hsl(0, 100%, 40%);">-config ZOOMBINI_USE_I2C_TPM</span><br><span style="color: hsl(0, 100%, 40%);">- bool</span><br><span style="color: hsl(0, 100%, 40%);">- default n</span><br><span style="color: hsl(0, 100%, 40%);">- select MAINBOARD_HAS_I2C_TPM_CR50</span><br><span style="color: hsl(0, 100%, 40%);">- select MAINBOARD_HAS_TPM2</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-# Select this option to enable use of cr50 SPI TPM on zoombini.</span><br><span style="color: hsl(0, 100%, 40%);">-config ZOOMBINI_USE_SPI_TPM</span><br><span style="color: hsl(0, 100%, 40%);">- bool</span><br><span style="color: hsl(0, 100%, 40%);">- default y</span><br><span style="color: hsl(0, 100%, 40%);">- select MAINBOARD_HAS_SPI_TPM_CR50</span><br><span style="color: hsl(0, 100%, 40%);">- select MAINBOARD_HAS_TPM2</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config TPM_TIS_ACPI_INTERRUPT</span><br><span style="color: hsl(0, 100%, 40%);">- int</span><br><span style="color: hsl(0, 100%, 40%);">- default 76 # GPE0_DW2_12 (GPP_C12)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-endif # BOARD_GOOGLE_BASEBOARD_ZOOMBINI</span><br><span>diff --git a/src/mainboard/google/zoombini/Kconfig.name b/src/mainboard/google/zoombini/Kconfig.name</span><br><span>deleted file mode 100644</span><br><span>index 6d4adcc..0000000</span><br><span>--- a/src/mainboard/google/zoombini/Kconfig.name</span><br><span>+++ /dev/null</span><br><span>@@ -1,11 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-comment "Zoombini"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config BOARD_GOOGLE_ZOOMBINI</span><br><span style="color: hsl(0, 100%, 40%);">- bool "-> Zoombini"</span><br><span style="color: hsl(0, 100%, 40%);">- select BOARD_GOOGLE_BASEBOARD_ZOOMBINI</span><br><span style="color: hsl(0, 100%, 40%);">- select BASEBOARD_ZOOMBINI_LAPTOP</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config BOARD_GOOGLE_MEOWTH</span><br><span style="color: hsl(0, 100%, 40%);">- bool "-> Meowth"</span><br><span style="color: hsl(0, 100%, 40%);">- select BOARD_GOOGLE_BASEBOARD_ZOOMBINI</span><br><span style="color: hsl(0, 100%, 40%);">- select BASEBOARD_ZOOMBINI_LAPTOP</span><br><span>diff --git a/src/mainboard/google/zoombini/Makefile.inc b/src/mainboard/google/zoombini/Makefile.inc</span><br><span>deleted file mode 100644</span><br><span>index d4e9fd4..0000000</span><br><span>--- a/src/mainboard/google/zoombini/Makefile.inc</span><br><span>+++ /dev/null</span><br><span>@@ -1,40 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## Copyright 2018 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">-## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">-## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">-## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">-## GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-bootblock-y += bootblock.c</span><br><span style="color: hsl(0, 100%, 40%);">-bootblock-$(CONFIG_CHROMEOS) += chromeos.c</span><br><span style="color: hsl(0, 100%, 40%);">-bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-verstage-$(CONFIG_CHROMEOS) += chromeos.c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-$(CONFIG_CHROMEOS) += chromeos.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += memory.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += romstage.c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-$(CONFIG_CHROMEOS) += chromeos.c</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += mainboard.c</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += ramstage.c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-subdirs-y += variants/baseboard</span><br><span style="color: hsl(0, 100%, 40%);">-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-subdirs-y += variants/$(VARIANT_DIR)</span><br><span style="color: hsl(0, 100%, 40%);">-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include</span><br><span style="color: hsl(0, 100%, 40%);">-subdirs-y += variants/$(VARIANT_DIR)/spd</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-subdirs-y += spd</span><br><span>diff --git a/src/mainboard/google/zoombini/acpi_tables.c b/src/mainboard/google/zoombini/acpi_tables.c</span><br><span>deleted file mode 100644</span><br><span>index e69de29..0000000</span><br><span>--- a/src/mainboard/google/zoombini/acpi_tables.c</span><br><span>+++ /dev/null</span><br><span>diff --git a/src/mainboard/google/zoombini/board_info.txt b/src/mainboard/google/zoombini/board_info.txt</span><br><span>deleted file mode 100644</span><br><span>index 3ed5a7e..0000000</span><br><span>--- a/src/mainboard/google/zoombini/board_info.txt</span><br><span>+++ /dev/null</span><br><span>@@ -1,6 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-Vendor name: Google</span><br><span style="color: hsl(0, 100%, 40%);">-Board name: Zoombini Cannonlake Reference Board</span><br><span style="color: hsl(0, 100%, 40%);">-Category: laptop</span><br><span style="color: hsl(0, 100%, 40%);">-ROM protocol: SPI</span><br><span style="color: hsl(0, 100%, 40%);">-ROM socketed: n</span><br><span style="color: hsl(0, 100%, 40%);">-Flashrom support: y</span><br><span>diff --git a/src/mainboard/google/zoombini/bootblock.c b/src/mainboard/google/zoombini/bootblock.c</span><br><span>deleted file mode 100644</span><br><span>index 5f37206..0000000</span><br><span>--- a/src/mainboard/google/zoombini/bootblock.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,33 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2017 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <baseboard/gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <baseboard/variants.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <bootblock_common.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void early_config_gpio(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- const struct pad_config *early_gpio_table;</span><br><span style="color: hsl(0, 100%, 40%);">- size_t num_gpios = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- early_gpio_table = variant_early_gpio_table(&num_gpios);</span><br><span style="color: hsl(0, 100%, 40%);">- gpio_configure_pads(early_gpio_table, num_gpios);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void bootblock_mainboard_init(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- early_config_gpio();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/google/zoombini/chromeos.c b/src/mainboard/google/zoombini/chromeos.c</span><br><span>deleted file mode 100644</span><br><span>index 730e2c4..0000000</span><br><span>--- a/src/mainboard/google/zoombini/chromeos.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,52 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2017 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/acpi.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <baseboard/gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <boot/coreboot_tables.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <rules.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <vendorcode/google/chromeos/chromeos.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void fill_lb_gpios(struct lb_gpios *gpios)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- struct lb_gpio chromeos_gpios[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},</span><br><span style="color: hsl(0, 100%, 40%);">- {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},</span><br><span style="color: hsl(0, 100%, 40%);">- {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},</span><br><span style="color: hsl(0, 100%, 40%);">- {-1, ACTIVE_HIGH, 0, "power"},</span><br><span style="color: hsl(0, 100%, 40%);">- {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},</span><br><span style="color: hsl(0, 100%, 40%);">- /* always report back 0 as temp workaround for b:74215817 */</span><br><span style="color: hsl(0, 100%, 40%);">- {GPIO_EC_IN_RW, ACTIVE_HIGH, 0, "EC in RW"},</span><br><span style="color: hsl(0, 100%, 40%);">- };</span><br><span style="color: hsl(0, 100%, 40%);">- lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-int get_write_protect_state(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Read PCH_WP GPIO. */</span><br><span style="color: hsl(0, 100%, 40%);">- return gpio_get(GPIO_PCH_WP);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static const struct cros_gpio cros_gpios[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),</span><br><span style="color: hsl(0, 100%, 40%);">- CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void mainboard_chromeos_acpi_generate(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/google/zoombini/chromeos.fmd b/src/mainboard/google/zoombini/chromeos.fmd</span><br><span>deleted file mode 100644</span><br><span>index 7123a5f..0000000</span><br><span>--- a/src/mainboard/google/zoombini/chromeos.fmd</span><br><span>+++ /dev/null</span><br><span>@@ -1,44 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-FLASH@0xff000000 0x1000000 {</span><br><span style="color: hsl(0, 100%, 40%);">- SI_ALL@0x0 0x300000 {</span><br><span style="color: hsl(0, 100%, 40%);">- SI_DESC@0x0 0x1000</span><br><span style="color: hsl(0, 100%, 40%);">- SI_ME@0x1000 0x2ff000</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- SI_BIOS@0x300000 0xd00000 {</span><br><span style="color: hsl(0, 100%, 40%);">- RW_SECTION_A@0x0 0x368000 {</span><br><span style="color: hsl(0, 100%, 40%);">- VBLOCK_A@0x0 0x10000</span><br><span style="color: hsl(0, 100%, 40%);">- FW_MAIN_A(CBFS)@0x10000 0x357fc0</span><br><span style="color: hsl(0, 100%, 40%);">- RW_FWID_A@0x367fc0 0x40</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- RW_SECTION_B@0x368000 0x368000 {</span><br><span style="color: hsl(0, 100%, 40%);">- VBLOCK_B@0x0 0x10000</span><br><span style="color: hsl(0, 100%, 40%);">- FW_MAIN_B(CBFS)@0x10000 0x357fc0</span><br><span style="color: hsl(0, 100%, 40%);">- RW_FWID_B@0x367fc0 0x40</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- RW_MISC@0x6d0000 0x30000 {</span><br><span style="color: hsl(0, 100%, 40%);">- UNIFIED_MRC_CACHE@0x0 0x20000 {</span><br><span style="color: hsl(0, 100%, 40%);">- RECOVERY_MRC_CACHE@0x0 0x10000</span><br><span style="color: hsl(0, 100%, 40%);">- RW_MRC_CACHE@0x10000 0x10000</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- RW_ELOG@0x20000 0x4000</span><br><span style="color: hsl(0, 100%, 40%);">- RW_SHARED@0x24000 0x4000 {</span><br><span style="color: hsl(0, 100%, 40%);">- SHARED_DATA@0x0 0x2000</span><br><span style="color: hsl(0, 100%, 40%);">- VBLOCK_DEV@0x2000 0x2000</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- RW_VPD@0x28000 0x2000</span><br><span style="color: hsl(0, 100%, 40%);">- RW_NVRAM@0x2a000 0x6000</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- SMMSTORE@0x700000 0x40000</span><br><span style="color: hsl(0, 100%, 40%);">- RW_LEGACY(CBFS)@0x740000 0x1c0000</span><br><span style="color: hsl(0, 100%, 40%);">- WP_RO@0x900000 0x400000 {</span><br><span style="color: hsl(0, 100%, 40%);">- RO_VPD@0x0 0x4000</span><br><span style="color: hsl(0, 100%, 40%);">- RO_UNUSED@0x4000 0xc000</span><br><span style="color: hsl(0, 100%, 40%);">- RO_SECTION@0x10000 0x3f0000 {</span><br><span style="color: hsl(0, 100%, 40%);">- FMAP@0x0 0x800</span><br><span style="color: hsl(0, 100%, 40%);">- RO_FRID@0x800 0x40</span><br><span style="color: hsl(0, 100%, 40%);">- RO_FRID_PAD@0x840 0x7c0</span><br><span style="color: hsl(0, 100%, 40%);">- GBB@0x1000 0xef000</span><br><span style="color: hsl(0, 100%, 40%);">- COREBOOT(CBFS)@0xf0000 0x300000</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/google/zoombini/dsdt.asl b/src/mainboard/google/zoombini/dsdt.asl</span><br><span>deleted file mode 100644</span><br><span>index e9988f0..0000000</span><br><span>--- a/src/mainboard/google/zoombini/dsdt.asl</span><br><span>+++ /dev/null</span><br><span>@@ -1,64 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2017 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2017 Intel Corporation</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include "variant/ec.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include "variant/gpio.h"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/acpi.h></span><br><span style="color: hsl(0, 100%, 40%);">-DefinitionBlock(</span><br><span style="color: hsl(0, 100%, 40%);">- "dsdt.aml",</span><br><span style="color: hsl(0, 100%, 40%);">- "DSDT",</span><br><span style="color: hsl(0, 100%, 40%);">- 0x02, // DSDT revision: ACPI v2.0 and up</span><br><span style="color: hsl(0, 100%, 40%);">- OEM_ID,</span><br><span style="color: hsl(0, 100%, 40%);">- ACPI_TABLE_CREATOR,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x20110725 // OEM revision</span><br><span style="color: hsl(0, 100%, 40%);">-)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- // Some generic macros</span><br><span style="color: hsl(0, 100%, 40%);">- #include <soc/intel/cannonlake/acpi/platform.asl></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // global NVS and variables</span><br><span style="color: hsl(0, 100%, 40%);">- #include <soc/intel/cannonlake/acpi/globalnvs.asl></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // CPU</span><br><span style="color: hsl(0, 100%, 40%);">- #include <cpu/intel/common/acpi/cpu.asl></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Scope (\_SB) {</span><br><span style="color: hsl(0, 100%, 40%);">- Device (PCI0)</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- #include <soc/intel/cannonlake/acpi/northbridge.asl></span><br><span style="color: hsl(0, 100%, 40%);">- #include <soc/intel/cannonlake/acpi/southbridge.asl></span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- #if IS_ENABLED(CONFIG_CHROMEOS)</span><br><span style="color: hsl(0, 100%, 40%);">- // Chrome OS specific</span><br><span style="color: hsl(0, 100%, 40%);">- #include <vendorcode/google/chromeos/acpi/chromeos.asl></span><br><span style="color: hsl(0, 100%, 40%);">- #endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // Chipset specific sleep states</span><br><span style="color: hsl(0, 100%, 40%);">- #include <soc/intel/cannonlake/acpi/sleepstates.asl></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Chrome OS Embedded Controller */</span><br><span style="color: hsl(0, 100%, 40%);">- Scope (\_SB.PCI0.LPCB)</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- /* ACPI code for EC SuperIO functions */</span><br><span style="color: hsl(0, 100%, 40%);">- #include <ec/google/chromeec/acpi/superio.asl></span><br><span style="color: hsl(0, 100%, 40%);">- /* ACPI code for EC functions */</span><br><span style="color: hsl(0, 100%, 40%);">- #include <ec/google/chromeec/acpi/ec.asl></span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/google/zoombini/ec.c b/src/mainboard/google/zoombini/ec.c</span><br><span>deleted file mode 100644</span><br><span>index d756444..0000000</span><br><span>--- a/src/mainboard/google/zoombini/ec.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,30 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2017 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/acpi.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <ec/google/chromeec/ec.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <variant/ec.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void mainboard_ec_init(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- const struct google_chromeec_event_info info = {</span><br><span style="color: hsl(0, 100%, 40%);">- .log_events = MAINBOARD_EC_LOG_EVENTS,</span><br><span style="color: hsl(0, 100%, 40%);">- .sci_events = MAINBOARD_EC_SCI_EVENTS,</span><br><span style="color: hsl(0, 100%, 40%);">- .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,</span><br><span style="color: hsl(0, 100%, 40%);">- .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,</span><br><span style="color: hsl(0, 100%, 40%);">- };</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- google_chromeec_events_init(&info, acpi_is_wakeup_s3());</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/google/zoombini/mainboard.c b/src/mainboard/google/zoombini/mainboard.c</span><br><span>deleted file mode 100644</span><br><span>index 96e1ac0..0000000</span><br><span>--- a/src/mainboard/google/zoombini/mainboard.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,61 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2017 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/device.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <ec/ec.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <vendorcode/google/chromeos/chromeos.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <nhlt.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/acpi.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <baseboard/variants.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void mainboard_init(struct device *dev)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- mainboard_ec_init();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static unsigned long mainboard_write_acpi_tables(struct device *device,</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned long current, acpi_rsdp_t *rsdp)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uintptr_t start_addr;</span><br><span style="color: hsl(0, 100%, 40%);">- uintptr_t end_addr;</span><br><span style="color: hsl(0, 100%, 40%);">- struct nhlt *nhlt;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- start_addr = current;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- nhlt = nhlt_init();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (nhlt == NULL)</span><br><span style="color: hsl(0, 100%, 40%);">- return start_addr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- variant_nhlt_init(nhlt);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- end_addr = nhlt_soc_serialize(nhlt, start_addr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (end_addr != start_addr)</span><br><span style="color: hsl(0, 100%, 40%);">- acpi_add_table(rsdp, (void *)start_addr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return end_addr;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void mainboard_enable(struct device *dev)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- dev->ops->init = mainboard_init;</span><br><span style="color: hsl(0, 100%, 40%);">- dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;</span><br><span style="color: hsl(0, 100%, 40%);">- dev->ops->write_acpi_tables = mainboard_write_acpi_tables;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-struct chip_operations mainboard_ops = {</span><br><span style="color: hsl(0, 100%, 40%);">- .enable_dev = mainboard_enable,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span>diff --git a/src/mainboard/google/zoombini/memory.c b/src/mainboard/google/zoombini/memory.c</span><br><span>deleted file mode 100644</span><br><span>index 60829b1..0000000</span><br><span>--- a/src/mainboard/google/zoombini/memory.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,97 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2017 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <baseboard/variants.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <baseboard/gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/cnl_memcfg_init.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static const struct cnl_mb_cfg baseboard_lpddr4_cfg = {</span><br><span style="color: hsl(0, 100%, 40%);">- .dq_map[DDR_CH0] = {</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * CLK0 goes to package 0 - Bytes[3:0],</span><br><span style="color: hsl(0, 100%, 40%);">- * CLK1 goes to package 1 - Bytes[7:4]</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- { 0x0F, 0xF0 },</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Cmd CAA goes to Bytes[3:0],</span><br><span style="color: hsl(0, 100%, 40%);">- * Cmd CAB goes to Bytes[7:4]</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- { 0x0F, 0xF0 },</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* CTL (CS) goes to all bytes */</span><br><span style="color: hsl(0, 100%, 40%);">- { 0xFF, 0x00 },</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- .dq_map[DDR_CH1] = {</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * CLK0 goes to package 0 - Bytes[3:0],</span><br><span style="color: hsl(0, 100%, 40%);">- * CLK1 goes to package 1 - Bytes[7:4]</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- { 0x0F, 0xF0 },</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Cmd CAA goes to Bytes[3:0],</span><br><span style="color: hsl(0, 100%, 40%);">- * Cmd CAB goes to Bytes[7:4]</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- { 0x0F, 0xF0 },</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* CTL (CS) goes to all bytes */</span><br><span style="color: hsl(0, 100%, 40%);">- { 0xFF, 0x00 },</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * The dqs_map arrays map the lpddr4 pins to the SoC pins</span><br><span style="color: hsl(0, 100%, 40%);">- * for both channels.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * the index = pin number on lpddr4 part</span><br><span style="color: hsl(0, 100%, 40%);">- * the value = pin number on SoC</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- .dqs_map[DDR_CH0] = { 3, 1, 2, 0, 7, 5, 6, 4 },</span><br><span style="color: hsl(0, 100%, 40%);">- .dqs_map[DDR_CH1] = { 3, 2, 0, 1, 7, 5, 6, 4 },</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Baseboard uses three 100 Ohm rcomp resistors */</span><br><span style="color: hsl(0, 100%, 40%);">- .rcomp_resistor = { 100, 100, 100 },</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Baseboard Rcomp target values.</span><br><span style="color: hsl(0, 100%, 40%);">- * Rcomp targets for baseboard should be</span><br><span style="color: hsl(0, 100%, 40%);">- * { 80, 40, 40, 40, 30 }, but we need to</span><br><span style="color: hsl(0, 100%, 40%);">- * nil out rcomp targets for now to avoid bug b:70896346</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- .rcomp_targets = { 0, 0, 0, 0, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Baseboard is a non-interleaved design */</span><br><span style="color: hsl(0, 100%, 40%);">- .dq_pins_interleaved = 0,</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable Early Command Training */</span><br><span style="color: hsl(0, 100%, 40%);">- .ect = 0,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-const struct cnl_mb_cfg *__weak variant_lpddr4_config(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return &baseboard_lpddr4_cfg;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-size_t __weak variant_memory_sku(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- const gpio_t pads[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- [3] = GPIO_MEM_CONFIG_3, [2] = GPIO_MEM_CONFIG_2,</span><br><span style="color: hsl(0, 100%, 40%);">- [1] = GPIO_MEM_CONFIG_1, [0] = GPIO_MEM_CONFIG_0,</span><br><span style="color: hsl(0, 100%, 40%);">- };</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return gpio_base2_value(pads, ARRAY_SIZE(pads));</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/google/zoombini/ramstage.c b/src/mainboard/google/zoombini/ramstage.c</span><br><span>deleted file mode 100644</span><br><span>index 7c73357..0000000</span><br><span>--- a/src/mainboard/google/zoombini/ramstage.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,27 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2017 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <baseboard/variants.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/ramstage.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <variant/gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void mainboard_silicon_init_params(FSP_S_CONFIG *params)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- size_t num;</span><br><span style="color: hsl(0, 100%, 40%);">- const struct pad_config *gpio_table;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- gpio_table = variant_gpio_table(&num);</span><br><span style="color: hsl(0, 100%, 40%);">- gpio_configure_pads(gpio_table, num);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/google/zoombini/romstage.c b/src/mainboard/google/zoombini/romstage.c</span><br><span>deleted file mode 100644</span><br><span>index 4bd0ede..0000000</span><br><span>--- a/src/mainboard/google/zoombini/romstage.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,29 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2017 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <baseboard/variants.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/cnl_memcfg_init.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/romstage.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void mainboard_memory_init_params(FSPM_UPD *memupd)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- const struct spd_info spd = {</span><br><span style="color: hsl(0, 100%, 40%);">- .spd_by_index = true,</span><br><span style="color: hsl(0, 100%, 40%);">- .spd_spec.spd_index = variant_memory_sku(),</span><br><span style="color: hsl(0, 100%, 40%);">- };</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- cannonlake_memcfg_init(&memupd->FspmConfig,</span><br><span style="color: hsl(0, 100%, 40%);">- variant_lpddr4_config(), &spd);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/google/zoombini/smihandler.c b/src/mainboard/google/zoombini/smihandler.c</span><br><span>deleted file mode 100644</span><br><span>index c9d08a5..0000000</span><br><span>--- a/src/mainboard/google/zoombini/smihandler.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,39 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2017 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/smm.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <ec/google/chromeec/smm.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/smm.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <variant/ec.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void mainboard_smi_espi_handler(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- chromeec_smi_process_events();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void mainboard_smi_sleep(u8 slp_typ)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,</span><br><span style="color: hsl(0, 100%, 40%);">- MAINBOARD_EC_S5_WAKE_EVENTS);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-int mainboard_smi_apmc(u8 apmc)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,</span><br><span style="color: hsl(0, 100%, 40%);">- MAINBOARD_EC_SMI_EVENTS);</span><br><span style="color: hsl(0, 100%, 40%);">- return 0;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/google/zoombini/spd/Hynix_H9HCNNN8KUMLHR_1GB.spd.hex b/src/mainboard/google/zoombini/spd/Hynix_H9HCNNN8KUMLHR_1GB.spd.hex</span><br><span>deleted file mode 100644</span><br><span>index b5da9f3..0000000</span><br><span>--- a/src/mainboard/google/zoombini/spd/Hynix_H9HCNNN8KUMLHR_1GB.spd.hex</span><br><span>+++ /dev/null</span><br><span>@@ -1,32 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-23 11 10 0E 15 19 05 08 00 40 00 00 02 22 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 05 FF 92 55 00 00 8C 00 90 A8 90 A0 05 D0</span><br><span style="color: hsl(0, 100%, 40%);">-02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 9E 00 A7 ED 8A</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span>diff --git a/src/mainboard/google/zoombini/spd/Hynix_H9HCNNNCPUMLHR_4GB.spd.hex b/src/mainboard/google/zoombini/spd/Hynix_H9HCNNNCPUMLHR_4GB.spd.hex</span><br><span>deleted file mode 100644</span><br><span>index 1a6d90bc..0000000</span><br><span>--- a/src/mainboard/google/zoombini/spd/Hynix_H9HCNNNCPUMLHR_4GB.spd.hex</span><br><span>+++ /dev/null</span><br><span>@@ -1,32 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-23 11 10 0E 16 21 95 08 00 40 00 00 0A 22 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-48 00 05 FF 92 55 00 00 A0 41 90 A8 90 A0 05 D0</span><br><span style="color: hsl(0, 100%, 40%);">-02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 7A 05</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span>diff --git a/src/mainboard/google/zoombini/spd/Makefile.inc b/src/mainboard/google/zoombini/spd/Makefile.inc</span><br><span>deleted file mode 100644</span><br><span>index 0aec18d..0000000</span><br><span>--- a/src/mainboard/google/zoombini/spd/Makefile.inc</span><br><span>+++ /dev/null</span><br><span>@@ -1,34 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## Copyright 2018 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">-## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">-## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">-## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">-## GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-SPD_BIN = $(obj)/spd.bin</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-ifeq ($(SPD_SOURCES),)</span><br><span style="color: hsl(0, 100%, 40%);">- SPD_DEPS := $(error SPD_SOURCES is not set. Variant must provide this)</span><br><span style="color: hsl(0, 100%, 40%);">-else</span><br><span style="color: hsl(0, 100%, 40%);">- SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)</span><br><span style="color: hsl(0, 100%, 40%);">-endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-# Include spd ROM data</span><br><span style="color: hsl(0, 100%, 40%);">-$(SPD_BIN): $(SPD_DEPS)</span><br><span style="color: hsl(0, 100%, 40%);">- for f in $+; \</span><br><span style="color: hsl(0, 100%, 40%);">- do for c in $$(cat $$f | grep -v ^#); \</span><br><span style="color: hsl(0, 100%, 40%);">- do printf $$(printf '\%o' 0x$$c); \</span><br><span style="color: hsl(0, 100%, 40%);">- done; \</span><br><span style="color: hsl(0, 100%, 40%);">- done > $@</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-cbfs-files-y += spd.bin</span><br><span style="color: hsl(0, 100%, 40%);">-spd.bin-file := $(SPD_BIN)</span><br><span style="color: hsl(0, 100%, 40%);">-spd.bin-type := spd</span><br><span>diff --git a/src/mainboard/google/zoombini/spd/Micron_MT53B1024M32D4_4GB.spd.hex b/src/mainboard/google/zoombini/spd/Micron_MT53B1024M32D4_4GB.spd.hex</span><br><span>deleted file mode 100644</span><br><span>index 1e28d92..0000000</span><br><span>--- a/src/mainboard/google/zoombini/spd/Micron_MT53B1024M32D4_4GB.spd.hex</span><br><span>+++ /dev/null</span><br><span>@@ -1,32 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-23 11 10 OE 15 21 B5 08 00 40 00 00 0A 63 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-51 00 05 FF D2 5D 01 00 A0 41 90 A8 90 A0 05 D0</span><br><span style="color: hsl(0, 100%, 40%);">-02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 7A 05</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span>diff --git a/src/mainboard/google/zoombini/spd/Micron_MT53B512M32D2_2GB.spd.hex b/src/mainboard/google/zoombini/spd/Micron_MT53B512M32D2_2GB.spd.hex</span><br><span>deleted file mode 100644</span><br><span>index 87d0420..0000000</span><br><span>--- a/src/mainboard/google/zoombini/spd/Micron_MT53B512M32D2_2GB.spd.hex</span><br><span>+++ /dev/null</span><br><span>@@ -1,32 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-23 11 10 OE 15 19 95 08 00 40 00 00 0A 63 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-09 00 04 00 D2 5D 05 00 89 41 90 A8 90 A0 05 D0</span><br><span style="color: hsl(0, 100%, 40%);">-02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 FB 00 23 17 9B</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 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00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span>diff --git a/src/mainboard/google/zoombini/spd/Samsung_K4F6E3S4HM_2GB.spd.hex b/src/mainboard/google/zoombini/spd/Samsung_K4F6E3S4HM_2GB.spd.hex</span><br><span>deleted file mode 100644</span><br><span>index f4c330a..0000000</span><br><span>--- a/src/mainboard/google/zoombini/spd/Samsung_K4F6E3S4HM_2GB.spd.hex</span><br><span>+++ /dev/null</span><br><span>@@ -1,32 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-23 10 10 0E 15 19 95 08 00 40 00 00 02 22 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-48 00 05 FF 92 55 00 00 8C 00 90 A8 90 A0 05 D0</span><br><span style="color: hsl(0, 100%, 40%);">-02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 55 00 00 00 20 20 20 20 20 20 20</span><br><span style="color: hsl(0, 100%, 40%);">-20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span>diff --git a/src/mainboard/google/zoombini/spd/Samsung_K4F8E304HB_1GB.spd.hex b/src/mainboard/google/zoombini/spd/Samsung_K4F8E304HB_1GB.spd.hex</span><br><span>deleted file mode 100644</span><br><span>index bf5e261..0000000</span><br><span>--- a/src/mainboard/google/zoombini/spd/Samsung_K4F8E304HB_1GB.spd.hex</span><br><span>+++ /dev/null</span><br><span>@@ -1,32 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-23 10 10 0E 15 19 04 08 00 00 00 00 02 22 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-48 00 05 0f 92 54 01 00 8A 00 90 A8 90 A0 05 D0</span><br><span style="color: hsl(0, 100%, 40%);">-02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 92 00 A7 E3 B5</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 4B 34 46 38 45 33 30</span><br><span style="color: hsl(0, 100%, 40%);">-34 48 42 2D 4D 47 43 6A 00 00 00 00 00 00 80 CE</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span>diff --git a/src/mainboard/google/zoombini/variants/baseboard/Makefile.inc b/src/mainboard/google/zoombini/variants/baseboard/Makefile.inc</span><br><span>deleted file mode 100644</span><br><span>index d81101a..0000000</span><br><span>--- a/src/mainboard/google/zoombini/variants/baseboard/Makefile.inc</span><br><span>+++ /dev/null</span><br><span>@@ -1,19 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## Copyright 2017 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">-## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">-## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">-## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">-## GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-bootblock-y += gpio.c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += gpio.c</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += nhlt.c</span><br><span>diff --git a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb</span><br><span>deleted file mode 100644</span><br><span>index 36c6595..0000000</span><br><span>--- a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb</span><br><span>+++ /dev/null</span><br><span>@@ -1,129 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-chip soc/intel/cannonlake</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- # GPE configuration</span><br><span style="color: hsl(0, 100%, 40%);">- # Note that GPE events called out in ASL code rely on this</span><br><span style="color: hsl(0, 100%, 40%);">- # route. i.e. If this route changes then the affected GPE</span><br><span style="color: hsl(0, 100%, 40%);">- # offset bits also need to be changed.</span><br><span style="color: hsl(0, 100%, 40%);">- register "gpe0_dw0" = "PMC_GPP_A"</span><br><span style="color: hsl(0, 100%, 40%);">- register "gpe0_dw1" = "PMC_GPP_B"</span><br><span style="color: hsl(0, 100%, 40%);">- register "gpe0_dw2" = "PMC_GPP_C"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f</span><br><span style="color: hsl(0, 100%, 40%);">- register "gen1_dec" = "0x00fc0801"</span><br><span style="color: hsl(0, 100%, 40%);">- register "gen2_dec" = "0x000c0201"</span><br><span style="color: hsl(0, 100%, 40%);">- # EC memory map range is 0x900-0x9ff</span><br><span style="color: hsl(0, 100%, 40%);">- register "gen3_dec" = "0x00fc0901"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- device cpu_cluster 0 on</span><br><span style="color: hsl(0, 100%, 40%);">- device lapic 0 on end</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- # FSP configuration</span><br><span style="color: hsl(0, 100%, 40%);">- register "SaGv" = "3"</span><br><span style="color: hsl(0, 100%, 40%);">- register "ScsEmmcHs400Enabled" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- # Intel Common SoC Config</span><br><span style="color: hsl(0, 100%, 40%);">- #+-------------------+---------------------------+</span><br><span style="color: hsl(0, 100%, 40%);">- #| Field | Value |</span><br><span style="color: hsl(0, 100%, 40%);">- #+-------------------+---------------------------+</span><br><span style="color: hsl(0, 100%, 40%);">- #| GSPI0 | cr50 TPM. Early init is |</span><br><span style="color: hsl(0, 100%, 40%);">- #| | required to set up a BAR |</span><br><span style="color: hsl(0, 100%, 40%);">- #| | for TPM communication |</span><br><span style="color: hsl(0, 100%, 40%);">- #| | before memory is up |</span><br><span style="color: hsl(0, 100%, 40%);">- #+-------------------+---------------------------+</span><br><span style="color: hsl(0, 100%, 40%);">- register "common_soc_config" = "{</span><br><span style="color: hsl(0, 100%, 40%);">- .gspi[0] = {</span><br><span style="color: hsl(0, 100%, 40%);">- .speed_mhz = 1,</span><br><span style="color: hsl(0, 100%, 40%);">- .early_init = 1,</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">- }"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[6]" = "USB2_PORT_TYPE_C(OC_SKIP)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[9]" = "USB2_PORT_TYPE_C(OC_SKIP)"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- # Enable Root port 8 (PCIe port 9) for NVMe</span><br><span style="color: hsl(0, 100%, 40%);">- register "PcieRpEnable[8]" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "PcieClkSrcUsage[3]" = "8"</span><br><span style="color: hsl(0, 100%, 40%);">- register "PcieClkSrcClkReq[3]" = "3"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- device domain 0 on</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 00.0 on end # Host Bridge</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 02.0 on end # Integrated Graphics Device</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 04.0 on end # SA Thermal device</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 12.0 on end # Thermal Subsystem</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 12.5 off end # UFS SCS</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 12.6 off end # GSPI #2</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 14.0 on end # USB xHCI</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 14.1 off end # USB xDCI (OTG)</span><br><span style="color: hsl(0, 100%, 40%);">- chip drivers/intel/wifi</span><br><span style="color: hsl(0, 100%, 40%);">- register "wake" = "PME_B0_EN_BIT"</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 14.3 on end # CNVi wifi</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 14.5 on end # SDCard</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 15.0 on end # I2C #0</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 15.1 on end # I2C #1</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 15.2 on end # I2C #2</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 15.3 on end # I2C #3</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 16.0 on end # Management Engine Interface 1</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 16.1 off end # Management Engine Interface 2</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 16.2 off end # Management Engine IDE-R</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 16.3 off end # Management Engine KT Redirection</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 16.4 off end # Management Engine Interface 3</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 16.5 off end # Management Engine Interface 4</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 17.0 off end # SATA</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 19.0 on end # I2C #4</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 19.1 on end # I2C #5</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 19.2 off end # UART #2</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1a.0 on end # eMMC</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1c.5 off end # PCI Express Port 6</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1c.6 off end # PCI Express Port 7</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1c.7 off end # PCI Express Port 8</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1d.0 on end # PCI Express Port 9</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1d.1 off end # PCI Express Port 10</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1d.2 off end # PCI Express Port 11</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1d.3 off end # PCI Express Port 12</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1d.4 off end # PCI Express Port 13</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1d.5 off end # PCI Express Port 14</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1d.6 off end # PCI Express Port 15</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1d.7 off end # PCI Express Port 16</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1e.0 on end # UART #0</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1e.1 off end # UART #1</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1e.2 on</span><br><span style="color: hsl(0, 100%, 40%);">- chip drivers/spi/acpi</span><br><span style="color: hsl(0, 100%, 40%);">- register "hid" = "ACPI_DT_NAMESPACE_HID"</span><br><span style="color: hsl(0, 100%, 40%);">- register "compat_string" = ""google,cr50""</span><br><span style="color: hsl(0, 100%, 40%);">- register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C12_IRQ)"</span><br><span style="color: hsl(0, 100%, 40%);">- device spi 0 on end</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- end # GSPI #0</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1e.3 on end # GSPI #1</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1f.0 on</span><br><span style="color: hsl(0, 100%, 40%);">- chip ec/google/chromeec</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 0c09.0 on end</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- end # LPC Interface</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1f.1 on end # P2SB</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1f.2 on end # Power Management Controller</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1f.3 on end # Intel HDA</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1f.4 on end # SMBus</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1f.5 on end # PCH SPI</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1f.6 off end # GbE</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">-end</span><br><span>diff --git a/src/mainboard/google/zoombini/variants/baseboard/gpio.c b/src/mainboard/google/zoombini/variants/baseboard/gpio.c</span><br><span>deleted file mode 100644</span><br><span>index 5447405..0000000</span><br><span>--- a/src/mainboard/google/zoombini/variants/baseboard/gpio.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,279 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2017 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <baseboard/gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <baseboard/variants.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Pad configuration in ramstage */</span><br><span style="color: hsl(0, 100%, 40%);">-static const struct pad_config gpio_table[] = {</span><br><span style="color: hsl(0, 100%, 40%);">-/* RCIN# */ PAD_CFG_GPI(GPP_A0, NONE, DEEP), /* PCH_CSI_GPIO1 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ESPI_IO0 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ESPI_IO1 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ESPI_IO2 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ESPI_IO3 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ESPI_CS# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SERIRQ */ PAD_CFG_GPI(GPP_A6, NONE, DEEP), /* PCH_CSI_GPIO2 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* PIRQA# */ PAD_NC(GPP_A7, NONE), /* PCH_CSI_GPIO1 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* CLKRUN# */ PAD_CFG_GPI(GPP_A8, NONE, DEEP), /* EC_IN_RW_OD */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ESPI_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">-/* CLKOUT_LPC1 */ PAD_CFG_GPO(GPP_A10, 0, DEEP), /* PEN_RESET_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* PME# */ PAD_NC(GPP_A11, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* BM_BUSY# */ PAD_CFG_GPI(GPP_A12, UP_20K, DEEP), /* FPMCU_INT */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SUSWARN# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ESPI_RESET# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SUSACK# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_PWR_EN# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_GP0 */ PAD_CFG_GPO(GPP_A18, 0, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">- /* GNSS_DISABLE_1V8_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_GP1 */ PAD_CFG_GPO(GPP_A19, 0, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">- /* WWAN_RADIO_DISABLE_1V8_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_GP2 */ PAD_CFG_GPI(GPP_A20, NONE, DEEP), /* GP_INT_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_GP3 */ PAD_CFG_GPI(GPP_A21, NONE, DEEP), /* FPMCU_PCH_BOOT0 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_GP4 */ PAD_CFG_GPI(GPP_A22, UP_20K, DEEP), /* FPMCU_INT */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_GP5 */ PAD_CFG_GPO(GPP_A23, 0, DEEP), /* FPMCU_RST_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* CORE_VID0 */ PAD_NC(GPP_B0, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* CORE_VID1 */ PAD_NC(GPP_B1, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* VRALERT# */ PAD_NC(GPP_B2, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* CPU_GP2 */ PAD_NC(GPP_B3, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* CPU_GP3 */ PAD_NC(GPP_B4, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SRCCLKREQ0# */ PAD_NC(GPP_B5, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SRCCLKREQ1# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SRCCLKREQ2# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SRCCLKREQ3# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SRCCLKREQ4# */ PAD_NC(GPP_B9, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* EXT_PWR_GATE# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SLP_S0# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* PLTRST# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SPKR */ PAD_NC(GPP_B14, DN_20K), /* GPP_B14_STRAP */</span><br><span style="color: hsl(0, 100%, 40%);">-#if IS_ENABLED(CONFIG_ZOOMBINI_USE_SPI_TPM)</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_CS# */ /* H1_SLAVE_SPI_CS_L */</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_CLK */ /* H1_SLAVE_SPI_CLK_R */</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_MISO */ /* H1_SLAVE_SPI_MISO_R */</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_MOSI */ /* H1_SLAVE_SPI_MOSI_R */</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_CLK */ PAD_NC(GPP_B16, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI1_CS# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI1_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI1_MISO */</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI1_MOSI */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SML1ALERT# */ PAD_NC(GPP_B23, DN_20K), /* GPP_B23_STRAP */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SMBCLK */ PAD_CFG_GPO(GPP_C0, 0, DEEP), /* SOC_EDP_CABC_EN */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SMBDATA */ PAD_CFG_GPI(GPP_C1, NONE, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">- /* PCIE_8_WLAN_WAKE_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SMBALERT# */ PAD_NC(GPP_C2, DN_20K), /* GPP_C2_STRAP - 20K_PD */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SML0CLK */ PAD_CFG_GPO(GPP_C3, 0, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">- /* EN_PP3300_TRACKPAD */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SML0DATA */ PAD_NC(GPP_C4, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SML0ALERT# */ PAD_NC(GPP_C5, DN_20K), /* GPP_C5_STRAP - 20K_PD */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SM1CLK */ PAD_CFG_GPI(GPP_C6, NONE, DEEP), /* PEN_PDCT_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SM1DATA */ PAD_CFG_GPI(GPP_C7, NONE, DEEP), /* PEN_INT_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART0_RXD */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART0_TXD */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART0_RTS# */ PAD_NC(GPP_C10, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART0_CTS# */ PAD_NC(GPP_C11, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART1_RXD */ PAD_CFG_GPI_APIC(GPP_C12, NONE, DEEP, EDGE_SINGLE,</span><br><span style="color: hsl(0, 100%, 40%);">- INVERT), /* H1_PCH_INT_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* TRACKPAD_INT_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">- /* TOUCHSCREEN_INT_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART1_CTS# */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* TRACKPAD_INT_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C0_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C0_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C1_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C1_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART2_RXD */ PAD_NC(GPP_C20, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART2_TXD */ PAD_NC(GPP_C21, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART2_RTS# */ PAD_NC(GPP_C22, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART2_CTS# */ PAD_NC(GPP_C23, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SPI1_CS# */ PAD_CFG_GPI(GPP_D0, NONE, DEEP), /* PCH_MEM_STRAP3 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SPI1_CLK */ PAD_NC(GPP_D1, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SPI1_MISO */ PAD_NC(GPP_D2, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SPI1_MOSI */ PAD_CFG_GPI(GPP_D3, NONE, DEEP), /* PCH_MEM_STRAP0 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* FASHTRIG */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* EC_I2C_SENSOR_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* EC_I2C_SENSOR_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_I2C1_SDA */ PAD_CFG_GPI(GPP_D7, NONE, DEEP), /* WWAN_SAR_INT_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_SPI_CS# */ PAD_CFG_GPO(GPP_D9, 0, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">- /* EN_PP3300_TOUCHSCREEN */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 0, DEEP), /* EN_PP3300_WLAN */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_SPI_MISO */ PAD_CFG_GPO(GPP_D11, 0, DEEP), /* EN_PP3300_WWAN */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_SPI_MOSI */ PAD_CFG_GPI(GPP_D12, NONE, DEEP), /* GPP_D12_STRAP */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), /* ISH_UART_RX */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), /* ISH_UART_TX */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 0, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">- /* TOUCHSCREEN_RST_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_UART0_CTS# */ PAD_CFG_GPO(GPP_D16, 0, DEEP), /* SPK_PA_EN */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* BASE_CAM_DMIC_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* BASE_CAM_DMIC_DATA */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* LID_CAM_DMIC_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* LID_CAM_DMIC_DATA */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SPI1_IO2 */ PAD_CFG_GPI(GPP_D21, NONE, DEEP), /* PCH_MEM_STRAP1 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SPI1_IO3 */ PAD_CFG_GPI(GPP_D22, NONE, DEEP), /* PCH_MEM_STRAP2 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2S_MCLK */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SATAXPCI0 */ PAD_NC(GPP_E0, NONE), /* PCH_TP_1 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), /* PCH_TP_2 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SATAXPCIE2 */ PAD_NC(GPP_E2, NONE), /* PCH_TP_3 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* CPU_GP0 */ PAD_NC(GPP_E3, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SATA_DEVSLP0 */ PAD_CFG_GPI(GPP_E4, NONE, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">- /* PCIE_7_WWAN_WAKE_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* CPU_GP1 */ PAD_NC(GPP_E7, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SATALED# */ PAD_NC(GPP_E8, NONE), /* PCH_TP_4 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* USB2_OCO# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* USB2_OC1# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* USB2_OC2# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* USB2_OC3# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPB_HPD0 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* USB_C1_HPD */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPD_HPD2 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* EDP_HPD */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPB_CTRLCLK */ PAD_NC(GPP_E18, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPB_CTRLDATA */ PAD_CFG_GPI(GPP_E19, DN_20K, DEEP), /* GPP_E19_STRAP */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPC_CTRLDATA */ PAD_CFG_GPI(GPP_E21, DN_20K, DEEP), /* GPP_E21_STRAP */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPD_CTRLDATA */ PAD_CFG_GPI(GPP_E23, DN_20K, DEEP), /* I2S2_SCLK */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2S2_SFRM */ PAD_CFG_GPO(GPP_F1, 0, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">- /* WWAN_RESET_1V8_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2S2_TXD */ PAD_NC(GPP_F2, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2S2_RXD */ PAD_CFG_GPO(GPP_F3, 0, DEEP), /* CNV_RF_RESET_L */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C2_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C2_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C3_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C3_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C4_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C4_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C5_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C5_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_CMD */</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_DATA0 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_DATA1 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_DATA2 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_DATA3 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_DATA4 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_DATA5 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_DATA6 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_DATA7 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_RCLK */</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">-/* RSVD */ PAD_NC(GPP_F23, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_CMD */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_DATA0 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_DATA1 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_DATA2 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_DATA3 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_CD# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), /* SD_CD_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2S2_SCLK */ PAD_NC(GPP_H0, NONE), /* I2S2_SCLK - TP75 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2S2_SFRM */ PAD_NC(GPP_H1, NONE), /* I2S2_SFRM - TP74 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2S2_TXD */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2S2_RXD */ PAD_NC(GPP_H3, NONE), /* I2S2_PCH_RX TP76 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C2_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C2_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C3_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C3_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C4_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C4_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C5_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C5_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* M2_SKT2_CFG0 */ PAD_NC(GPP_H12, NONE), /* PCH_TP_5 - TP60 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE), /* PCH_TP_6 - TP61 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), /* PCH_TP_7 - TP62 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* M2_SKT2_CFG3 */ PAD_NC(GPP_H15, NONE), /* PCH_TP_8 - TP63 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* DPPF_CTRLDATA */ PAD_NC(GPP_H17, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* CPU_C10_GATE# */ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* CPU_C10_GATE_PCH_L */</span><br><span style="color: hsl(0, 100%, 40%);">-/* TIMESYNC0 */ PAD_NC(GPP_H19, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* IMGCLKOUT1 */ PAD_NC(GPP_H20, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* GPP_H21 */ PAD_CFG_GPI(GPP_H21, DN_20K, DEEP), /* H21_STRAP */</span><br><span style="color: hsl(0, 100%, 40%);">-/* GPP_H22 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* GPP_H23 */ PAD_NC(GPP_H23, DN_20K), /* H23_STRAP */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* BATLOW# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ACPRESENT */ PAD_NC(GPD1, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* PWRBTN# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SLP_S3# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SLP_S4# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SLP_A# */ PAD_NC(GPD6, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* RSVD */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SUSCLK */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SLP_WLAN# */ PAD_NC(GPD9, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SLP_S5# */ PAD_NC(GPD10, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* LANPHYC */ PAD_NC(GPD11, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Early pad configuration in bootblock */</span><br><span style="color: hsl(0, 100%, 40%);">-static const struct pad_config early_gpio_table[] = {</span><br><span style="color: hsl(0, 100%, 40%);">-#if IS_ENABLED(CONFIG_ZOOMBINI_USE_SPI_TPM)</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_SPI_H1_3V3_CS_L */</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_SPI_H1_3V3_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_SPI_H1_3V3_MISO */</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_SPI_H1_3V3_MOSI */</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-#if IS_ENABLED(CONFIG_ZOOMBINI_USE_I2C_TPM)</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C5_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C5_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-/* Ensure UART pins are in native mode for H1. */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART0_RXD */ /* UART_PCH_RX_DEBUG_TX */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART0_TXD */ /* UART_PCH_RX_DEBUG_RX */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART1_RXD */ PAD_CFG_GPI_APIC(GPP_C12, NONE, DEEP, EDGE_SINGLE,</span><br><span style="color: hsl(0, 100%, 40%);">- INVERT), /* H1_PCH_INT_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-const struct pad_config *__weak variant_gpio_table(size_t *num)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- *num = ARRAY_SIZE(gpio_table);</span><br><span style="color: hsl(0, 100%, 40%);">- return gpio_table;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-const struct pad_config *__weak</span><br><span style="color: hsl(0, 100%, 40%);">- variant_early_gpio_table(size_t *num)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- *num = ARRAY_SIZE(early_gpio_table);</span><br><span style="color: hsl(0, 100%, 40%);">- return early_gpio_table;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static const struct cros_gpio cros_gpios[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-const struct cros_gpio *__weak variant_cros_gpios(size_t *num)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- *num = ARRAY_SIZE(cros_gpios);</span><br><span style="color: hsl(0, 100%, 40%);">- return cros_gpios;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/acpi/dptf.asl</span><br><span>deleted file mode 100644</span><br><span>index aba1385..0000000</span><br><span>--- a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/acpi/dptf.asl</span><br><span>+++ /dev/null</span><br><span>@@ -1,86 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2017 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2015 Intel Corporation.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPTF_CPU_PASSIVE 95</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPTF_CPU_CRITICAL 105</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPTF_CPU_ACTIVE_AC0 90</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPTF_CPU_ACTIVE_AC1 80</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPTF_CPU_ACTIVE_AC2 70</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPTF_CPU_ACTIVE_AC3 60</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPTF_CPU_ACTIVE_AC4 50</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPTF_TSR0_SENSOR_ID 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPTF_TSR0_SENSOR_NAME "Battery"</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPTF_TSR0_PASSIVE 120</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPTF_TSR0_CRITICAL 125</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPTF_TSR1_SENSOR_ID 1</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPTF_TSR1_SENSOR_NAME "Ambient"</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPTF_TSR1_PASSIVE 46</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPTF_TSR1_CRITICAL 75</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPTF_TSR2_SENSOR_ID 2</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPTF_TSR2_SENSOR_NAME "Charger"</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPTF_TSR2_PASSIVE 58</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPTF_TSR2_CRITICAL 90</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPTF_ENABLE_CHARGER</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Charger performance states, board-specific values from charger and EC */</span><br><span style="color: hsl(0, 100%, 40%);">-Name (CHPS, Package () {</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */</span><br><span style="color: hsl(0, 100%, 40%);">-})</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-Name (DTRT, Package () {</span><br><span style="color: hsl(0, 100%, 40%);">- /* CPU Throttle Effect on CPU */</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 100, 0, 0, 0, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* CPU Effect on Temp Sensor 0 */</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 1200, 0, 0, 0, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifdef DPTF_ENABLE_CHARGER</span><br><span style="color: hsl(0, 100%, 40%);">- /* Charger Effect on Temp Sensor 2 */</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 300, 0, 0, 0, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* CPU Effect on Temp Sensor 1 */</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 150, 0, 0, 0, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">-})</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-Name (MPPC, Package ()</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- 0x2, /* Revision */</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { /* Power Limit 1 */</span><br><span style="color: hsl(0, 100%, 40%);">- 0, /* PowerLimitIndex, 0 for Power Limit 1 */</span><br><span style="color: hsl(0, 100%, 40%);">- 3000, /* PowerLimitMinimum */</span><br><span style="color: hsl(0, 100%, 40%);">- 12000, /* PowerLimitMaximum */</span><br><span style="color: hsl(0, 100%, 40%);">- 1000, /* TimeWindowMinimum */</span><br><span style="color: hsl(0, 100%, 40%);">- 1000, /* TimeWindowMaximum */</span><br><span style="color: hsl(0, 100%, 40%);">- 200 /* StepSize */</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { /* Power Limit 2 */</span><br><span style="color: hsl(0, 100%, 40%);">- 1, /* PowerLimitIndex, 1 for Power Limit 2 */</span><br><span style="color: hsl(0, 100%, 40%);">- 8000, /* PowerLimitMinimum */</span><br><span style="color: hsl(0, 100%, 40%);">- 15000, /* PowerLimitMaximum */</span><br><span style="color: hsl(0, 100%, 40%);">- 1000, /* TimeWindowMinimum */</span><br><span style="color: hsl(0, 100%, 40%);">- 1000, /* TimeWindowMaximum */</span><br><span style="color: hsl(0, 100%, 40%);">- 1000 /* StepSize */</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-})</span><br><span>diff --git a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/ec.h</span><br><span>deleted file mode 100644</span><br><span>index 9766c1d..0000000</span><br><span>--- a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/ec.h</span><br><span>+++ /dev/null</span><br><span>@@ -1,82 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2017 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef __BASEBOARD_EC_H__</span><br><span style="color: hsl(0, 100%, 40%);">-#define __BASEBOARD_EC_H__</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <ec/ec.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <ec/google/chromeec/ec_commands.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include "gpio.h"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define MAINBOARD_EC_SCI_EVENTS \</span><br><span style="color: hsl(0, 100%, 40%);">- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define MAINBOARD_EC_SMI_EVENTS \</span><br><span style="color: hsl(0, 100%, 40%);">- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* EC can wake from S5 with lid or power button */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MAINBOARD_EC_S5_WAKE_EVENTS \</span><br><span style="color: hsl(0, 100%, 40%);">- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * EC can wake from S3 with lid or power button or key press or</span><br><span style="color: hsl(0, 100%, 40%);">- * mode change event.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MAINBOARD_EC_S3_WAKE_EVENTS \</span><br><span style="color: hsl(0, 100%, 40%);">- (MAINBOARD_EC_S5_WAKE_EVENTS |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Log EC wake events plus EC shutdown events */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MAINBOARD_EC_LOG_EVENTS \</span><br><span style="color: hsl(0, 100%, 40%);">- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * ACPI related definitions for ASL code.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Enable EC backed ALS device in ACPI */</span><br><span style="color: hsl(0, 100%, 40%);">-#define EC_ENABLE_ALS_DEVICE</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Enable EC backed PD MCU device in ACPI */</span><br><span style="color: hsl(0, 100%, 40%);">-#define EC_ENABLE_PD_MCU_DEVICE</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Enable LID switch and provide wake pin for EC */</span><br><span style="color: hsl(0, 100%, 40%);">-#define EC_ENABLE_LID_SWITCH</span><br><span style="color: hsl(0, 100%, 40%);">-#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define EC_ENABLE_MKBP_DEVICE /* Enable cros_ec_keyb device */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span>diff --git a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h</span><br><span>deleted file mode 100644</span><br><span>index f1460d2..0000000</span><br><span>--- a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h</span><br><span>+++ /dev/null</span><br><span>@@ -1,39 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2017 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef __BASEBOARD_GPIO_H__</span><br><span style="color: hsl(0, 100%, 40%);">-#define __BASEBOARD_GPIO_H__</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/gpe.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Memory configuration board straps */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_MEM_CONFIG_0 GPP_D3</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_MEM_CONFIG_1 GPP_D21</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_MEM_CONFIG_2 GPP_D22</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_MEM_CONFIG_3 GPP_D0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* EC in RW */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_EC_IN_RW GPP_A8</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* BIOS Flash Write Protect */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_PCH_WP GPP_H12</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPE_EC_WAKE GPE0_LAN_WAK</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* eSPI virtual wire reporting */</span><br><span style="color: hsl(0, 100%, 40%);">-#define EC_SCI_GPI GPE0_ESPI</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span>diff --git a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h</span><br><span>deleted file mode 100644</span><br><span>index e8c7c20..0000000</span><br><span>--- a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h</span><br><span>+++ /dev/null</span><br><span>@@ -1,47 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2017 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2017 Intel Corporation.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef __BASEBOARD_VARIANTS_H__</span><br><span style="color: hsl(0, 100%, 40%);">-#define __BASEBOARD_VARIANTS_H__</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/cnl_memcfg_init.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <stdint.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <vendorcode/google/chromeos/chromeos.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Return the board id for the current variant board. */</span><br><span style="color: hsl(0, 100%, 40%);">-int variant_board_id(void);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * The next set of functions return the gpio table and fill in the number of</span><br><span style="color: hsl(0, 100%, 40%);">- * entries for each table.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-const struct pad_config *variant_gpio_table(size_t *num);</span><br><span style="color: hsl(0, 100%, 40%);">-const struct pad_config *variant_early_gpio_table(size_t *num);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-const struct cros_gpio *variant_cros_gpios(size_t *num);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Return LPDDR4 configuration structure. */</span><br><span style="color: hsl(0, 100%, 40%);">-const struct cnl_mb_cfg *variant_lpddr4_config(void);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Return memory SKU for the board. */</span><br><span style="color: hsl(0, 100%, 40%);">-size_t variant_memory_sku(void);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Seed the NHLT tables with the board specific information. */</span><br><span style="color: hsl(0, 100%, 40%);">-struct nhlt;</span><br><span style="color: hsl(0, 100%, 40%);">-void variant_nhlt_init(struct nhlt *nhlt);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#endif /*__BASEBOARD_VARIANTS_H__ */</span><br><span>diff --git a/src/mainboard/google/zoombini/variants/baseboard/nhlt.c b/src/mainboard/google/zoombini/variants/baseboard/nhlt.c</span><br><span>deleted file mode 100644</span><br><span>index 84c1ec5..0000000</span><br><span>--- a/src/mainboard/google/zoombini/variants/baseboard/nhlt.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,52 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2017 Intel Corp.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <baseboard/variants.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <nhlt.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/nhlt.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void __weak variant_nhlt_init(struct nhlt *nhlt)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* 1-dmic configuration */</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_NHLT_DMIC_1CH_16B) &&</span><br><span style="color: hsl(0, 100%, 40%);">- !nhlt_soc_add_dmic_array(nhlt, 1))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Added 1CH DMIC array.\n");</span><br><span style="color: hsl(0, 100%, 40%);">- /* 2-dmic configuration */</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_NHLT_DMIC_2CH_16B) &&</span><br><span style="color: hsl(0, 100%, 40%);">- !nhlt_soc_add_dmic_array(nhlt, 2))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Added 2CH DMIC array.\n");</span><br><span style="color: hsl(0, 100%, 40%);">- /* 4-dmic configuration */</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_NHLT_DMIC_4CH_16B) &&</span><br><span style="color: hsl(0, 100%, 40%);">- !nhlt_soc_add_dmic_array(nhlt, 4))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Added 4CH DMIC array.\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_INCLUDE_SND_MAX98357_DA7219_NHLT)) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Dialog for Headset codec. Headset codec is bi-directional</span><br><span style="color: hsl(0, 100%, 40%);">- but uses the same configuration settings for render and</span><br><span style="color: hsl(0, 100%, 40%);">- capture endpoints. */</span><br><span style="color: hsl(0, 100%, 40%);">- if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP2))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Added Dialog_7219 codec.\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* MAXIM Smart Amps for left and right speakers. */</span><br><span style="color: hsl(0, 100%, 40%);">- if (!nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP1))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Added Maxim_98357 codec.\n");</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_INCLUDE_SND_MAX98373_NHLT) &&</span><br><span style="color: hsl(0, 100%, 40%);">- !nhlt_soc_add_max98373(nhlt, AUDIO_LINK_SSP1))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Added Maxim_98373 codec.\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/google/zoombini/variants/meowth/Makefile.inc b/src/mainboard/google/zoombini/variants/meowth/Makefile.inc</span><br><span>deleted file mode 100644</span><br><span>index 38653f1..0000000</span><br><span>--- a/src/mainboard/google/zoombini/variants/meowth/Makefile.inc</span><br><span>+++ /dev/null</span><br><span>@@ -1,25 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## Copyright 2018 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">-## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">-## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">-## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">-## GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-SPD_SOURCES = Samsung_K4F8E304HB_1GB # 0b000</span><br><span style="color: hsl(0, 100%, 40%);">-SPD_SOURCES += Hynix_H9HCNNN8KUMLHR_1GB # 0b001</span><br><span style="color: hsl(0, 100%, 40%);">-SPD_SOURCES += Samsung_K4F6E3S4HM_2GB # 0b010</span><br><span style="color: hsl(0, 100%, 40%);">-SPD_SOURCES += Hynix_H9HCNNNCPUMLHR_4GB # 0b011</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-bootblock-y += gpio.c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += memory.c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += gpio.c</span><br><span>diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb</span><br><span>deleted file mode 100644</span><br><span>index b014353..0000000</span><br><span>--- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb</span><br><span>+++ /dev/null</span><br><span>@@ -1,204 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-chip soc/intel/cannonlake</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- # Deep Sx states</span><br><span style="color: hsl(0, 100%, 40%);">- register "deep_s3_enable_ac" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">- register "deep_s3_enable_dc" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">- register "deep_s5_enable_ac" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "deep_s5_enable_dc" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- # Debug Option</span><br><span style="color: hsl(0, 100%, 40%);">- register "DebugConsent" = "DebugConsent_Disabled"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- # GPE configuration</span><br><span style="color: hsl(0, 100%, 40%);">- # Note that GPE events called out in ASL code rely on this</span><br><span style="color: hsl(0, 100%, 40%);">- # route. i.e. If this route changes then the affected GPE</span><br><span style="color: hsl(0, 100%, 40%);">- # offset bits also need to be changed.</span><br><span style="color: hsl(0, 100%, 40%);">- register "gpe0_dw0" = "PMC_GPP_A"</span><br><span style="color: hsl(0, 100%, 40%);">- register "gpe0_dw1" = "PMC_GPP_B"</span><br><span style="color: hsl(0, 100%, 40%);">- register "gpe0_dw2" = "PMC_GPP_C"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f</span><br><span style="color: hsl(0, 100%, 40%);">- register "gen1_dec" = "0x00fc0801"</span><br><span style="color: hsl(0, 100%, 40%);">- register "gen2_dec" = "0x000c0201"</span><br><span style="color: hsl(0, 100%, 40%);">- # EC memory map range is 0x900-0x9ff</span><br><span style="color: hsl(0, 100%, 40%);">- register "gen3_dec" = "0x00fc0901"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- device cpu_cluster 0 on</span><br><span style="color: hsl(0, 100%, 40%);">- device lapic 0 on end</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- # FSP configuration</span><br><span style="color: hsl(0, 100%, 40%);">- register "SaGv" = "SaGv_Enabled"</span><br><span style="color: hsl(0, 100%, 40%);">- register "ScsEmmcHs400Enabled" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- # Intel Common SoC Config</span><br><span style="color: hsl(0, 100%, 40%);">- #+-------------------+---------------------------+</span><br><span style="color: hsl(0, 100%, 40%);">- #| Field | Value |</span><br><span style="color: hsl(0, 100%, 40%);">- #+-------------------+---------------------------+</span><br><span style="color: hsl(0, 100%, 40%);">- #| GSPI0 | cr50 TPM. Early init is |</span><br><span style="color: hsl(0, 100%, 40%);">- #| | required to set up a BAR |</span><br><span style="color: hsl(0, 100%, 40%);">- #| | for TPM communication |</span><br><span style="color: hsl(0, 100%, 40%);">- #| | before memory is up |</span><br><span style="color: hsl(0, 100%, 40%);">- #| I2C0 | Touchscreen Digitizer |</span><br><span style="color: hsl(0, 100%, 40%);">- #+-------------------+---------------------------+</span><br><span style="color: hsl(0, 100%, 40%);">- register "common_soc_config" = "{</span><br><span style="color: hsl(0, 100%, 40%);">- .gspi[0] = {</span><br><span style="color: hsl(0, 100%, 40%);">- .speed_mhz = 1,</span><br><span style="color: hsl(0, 100%, 40%);">- .early_init = 1,</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">- .i2c[0] = {</span><br><span style="color: hsl(0, 100%, 40%);">- .speed = I2C_SPEED_FAST_PLUS,</span><br><span style="color: hsl(0, 100%, 40%);">- .rise_time_ns = 98,</span><br><span style="color: hsl(0, 100%, 40%);">- .fall_time_ns = 38,</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">- }"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC3)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[6]" = "USB2_PORT_TYPE_C(OC_SKIP)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb2_ports[9]" = "USB2_PORT_TYPE_C(OC_SKIP)"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- register "PchHdaDspEnable" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "PchHdaAudioLinkSsp0" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "PchHdaAudioLinkSsp1" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- # Enable cpufreq</span><br><span style="color: hsl(0, 100%, 40%);">- register "speed_shift_enable" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- # Enable Root port 8 (PCIe port 9) for NVMe</span><br><span style="color: hsl(0, 100%, 40%);">- register "PcieRpEnable[8]" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "PcieClkSrcUsage[3]" = "8"</span><br><span style="color: hsl(0, 100%, 40%);">- register "PcieClkSrcClkReq[3]" = "3"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- # Enable S0ix</span><br><span style="color: hsl(0, 100%, 40%);">- register "s0ix_enable" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- device domain 0 on</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 00.0 on end # Host Bridge</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 02.0 on end # Integrated Graphics Device</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 04.0 on end # SA Thermal device</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 12.0 on end # Thermal Subsystem</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 12.5 off end # UFS SCS</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 12.6 off end # GSPI #2</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 14.0 on end # USB xHCI</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 14.1 off end # USB xDCI (OTG)</span><br><span style="color: hsl(0, 100%, 40%);">- chip drivers/intel/wifi</span><br><span style="color: hsl(0, 100%, 40%);">- register "wake" = "PME_B0_EN_BIT"</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 14.3 on end # CNVi wifi</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 14.5 off end # SDCard</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 15.0 on</span><br><span style="color: hsl(0, 100%, 40%);">- chip drivers/i2c/hid</span><br><span style="color: hsl(0, 100%, 40%);">- register "generic.hid" = ""WCOM50C1""</span><br><span style="color: hsl(0, 100%, 40%);">- register "generic.desc" = ""WCOM Digitizer""</span><br><span style="color: hsl(0, 100%, 40%);">- register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C14_IRQ)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "generic.speed" = "I2C_SPEED_FAST_PLUS"</span><br><span style="color: hsl(0, 100%, 40%);">- register "hid_desc_reg_offset" = "0x1"</span><br><span style="color: hsl(0, 100%, 40%);">- device i2c 0a on end</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- end # I2C #0</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 15.1 on</span><br><span style="color: hsl(0, 100%, 40%);">- chip drivers/i2c/generic</span><br><span style="color: hsl(0, 100%, 40%);">- register "hid" = ""STH9310""</span><br><span style="color: hsl(0, 100%, 40%);">- register "name" = ""SEMTECH SX9310""</span><br><span style="color: hsl(0, 100%, 40%);">- register "desc" = ""Left SAR Proximity Sensor""</span><br><span style="color: hsl(0, 100%, 40%);">- register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C3_IRQ)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "speed" = "I2C_SPEED_FAST_PLUS"</span><br><span style="color: hsl(0, 100%, 40%);">- register "uid" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- device i2c 28 on end</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- end # I2C #1</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 15.2 on end # I2C #2</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 15.3 on</span><br><span style="color: hsl(0, 100%, 40%);">- chip drivers/i2c/max98373</span><br><span style="color: hsl(0, 100%, 40%);">- register "vmon_slot_no" = "4"</span><br><span style="color: hsl(0, 100%, 40%);">- register "imon_slot_no" = "5"</span><br><span style="color: hsl(0, 100%, 40%);">- register "uid" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">- register "desc" = ""RIGHT SPEAKER AMP""</span><br><span style="color: hsl(0, 100%, 40%);">- register "name" = ""MAXR""</span><br><span style="color: hsl(0, 100%, 40%);">- device i2c 31 on end</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- chip drivers/i2c/max98373</span><br><span style="color: hsl(0, 100%, 40%);">- register "vmon_slot_no" = "6"</span><br><span style="color: hsl(0, 100%, 40%);">- register "imon_slot_no" = "7"</span><br><span style="color: hsl(0, 100%, 40%);">- register "uid" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "desc" = ""LEFT SPEAKER AMP""</span><br><span style="color: hsl(0, 100%, 40%);">- register "name" = ""MAXL""</span><br><span style="color: hsl(0, 100%, 40%);">- device i2c 32 on end</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- end # I2C #3</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 16.0 on end # Management Engine Interface 1</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 16.1 off end # Management Engine Interface 2</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 16.2 off end # Management Engine IDE-R</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 16.3 off end # Management Engine KT Redirection</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 16.4 off end # Management Engine Interface 3</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 16.5 off end # Management Engine Interface 4</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 17.0 off end # SATA</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 19.0 on end # I2C #4</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 19.1 on</span><br><span style="color: hsl(0, 100%, 40%);">- chip drivers/i2c/generic</span><br><span style="color: hsl(0, 100%, 40%);">- register "hid" = ""STH9310""</span><br><span style="color: hsl(0, 100%, 40%);">- register "name" = ""SEMTECH SX9310""</span><br><span style="color: hsl(0, 100%, 40%);">- register "desc" = ""Right SAR Proximity Sensor""</span><br><span style="color: hsl(0, 100%, 40%);">- register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C4_IRQ)"</span><br><span style="color: hsl(0, 100%, 40%);">- register "speed" = "I2C_SPEED_FAST_PLUS"</span><br><span style="color: hsl(0, 100%, 40%);">- register "uid" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">- device i2c 28 on end</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- end # I2C #5</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 19.2 on end # UART #2</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1a.0 on end # eMMC</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1c.5 off end # PCI Express Port 6</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1c.6 off end # PCI Express Port 7</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1c.7 off end # PCI Express Port 8</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1d.0 on end # PCI Express Port 9</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1d.1 off end # PCI Express Port 10</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1d.2 off end # PCI Express Port 11</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1d.3 off end # PCI Express Port 12</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1d.4 off end # PCI Express Port 13</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1d.5 off end # PCI Express Port 14</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1d.6 off end # PCI Express Port 15</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1d.7 off end # PCI Express Port 16</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1e.0 on end # UART #0</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1e.1 off end # UART #1</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1e.2 on</span><br><span style="color: hsl(0, 100%, 40%);">- chip drivers/spi/acpi</span><br><span style="color: hsl(0, 100%, 40%);">- register "hid" = "ACPI_DT_NAMESPACE_HID"</span><br><span style="color: hsl(0, 100%, 40%);">- register "compat_string" = ""google,cr50""</span><br><span style="color: hsl(0, 100%, 40%);">- register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C12_IRQ)"</span><br><span style="color: hsl(0, 100%, 40%);">- device spi 0 on end</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- end # GSPI #0</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1e.3 on</span><br><span style="color: hsl(0, 100%, 40%);">- chip drivers/spi/acpi</span><br><span style="color: hsl(0, 100%, 40%);">- register "hid" = "ACPI_DT_NAMESPACE_HID"</span><br><span style="color: hsl(0, 100%, 40%);">- register "uid" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "compat_string" = ""google,cros-ec-spi""</span><br><span style="color: hsl(0, 100%, 40%);">- register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A22_IRQ)"</span><br><span style="color: hsl(0, 100%, 40%);">- device spi 0 on end</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- end # GSPI #1</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1f.0 on</span><br><span style="color: hsl(0, 100%, 40%);">- chip ec/google/chromeec</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 0c09.0 on end</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- end # LPC Interface</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1f.1 on end # P2SB</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1f.2 on end # Power Management Controller</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1f.3 on end # Intel HDA</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1f.4 on end # SMBus</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1f.5 on end # PCH SPI</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1f.6 off end # GbE</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">-end</span><br><span>diff --git a/src/mainboard/google/zoombini/variants/meowth/gpio.c b/src/mainboard/google/zoombini/variants/meowth/gpio.c</span><br><span>deleted file mode 100644</span><br><span>index 0f356e4..0000000</span><br><span>--- a/src/mainboard/google/zoombini/variants/meowth/gpio.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,289 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2017 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <baseboard/gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <baseboard/variants.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Pad configuration in ramstage */</span><br><span style="color: hsl(0, 100%, 40%);">-static const struct pad_config gpio_table[] = {</span><br><span style="color: hsl(0, 100%, 40%);">-/* RCIN# */ PAD_NC(GPP_A0, NONE), /* PCH_CSI_GPIO1 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ESPI_IO0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF2), /* ESPI_IO0_R */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ESPI_IO1 */ PAD_CFG_NF(GPP_A2, NONE, DEEP, NF2), /* ESPI_IO0_R */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ESPI_IO2 */ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF2), /* ESPI_IO2_R */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ESPI_IO3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF2), /* ESPI_IO3_R */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ESPI_CS# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF2), /* ESPI_CS_L */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SERIRQ */ PAD_NC(GPP_A6, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* PIRQA# */ PAD_NC(GPP_A7, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* CLKRUN# */ PAD_CFG_GPI(GPP_A8, NONE, DEEP), /* EC_IN_RW_OD */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ESPI_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF2), /* ESPI_CLK_R */</span><br><span style="color: hsl(0, 100%, 40%);">-/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* PME# */ PAD_CFG_GPO(GPP_A11, 1, DEEP), /* PCH_FP_PWR_EN */</span><br><span style="color: hsl(0, 100%, 40%);">-/* BM_BUSY# */ PAD_CFG_GPI(GPP_A12, NONE, DEEP), /* FPMCU_INT */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* SUSWARN_L */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ESPI_RESET# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF2), /* ESPI_RESET_L */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* SUSACK_L */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_GP0 */ PAD_NC(GPP_A18, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_GP1 */ PAD_NC(GPP_A19, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_GP2 */ PAD_NC(GPP_A20, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_GP3 */ PAD_CFG_GPO(GPP_A21, 0, DEEP), /* PCH_FPMCU_BOOT0 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_GP4 */ PAD_CFG_GPI_APIC(GPP_A22, NONE, DEEP, LEVEL,</span><br><span style="color: hsl(0, 100%, 40%);">- NONE), /* FPMCU_INT */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_GP5 */ PAD_CFG_GPO(GPP_A23, 1, DEEP), /* PCH_FPMCU_RST_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* CORE_VID0 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* CORE_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* CORE_VID1 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* VRALERT# */ PAD_NC(GPP_B2, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* CPU_GP2 */ PAD_NC(GPP_B3, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* CPU_GP3 */ PAD_NC(GPP_B4, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SRCCLKREQ0# */ PAD_NC(GPP_B5, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SRCCLKREQ1# */ PAD_NC(GPP_B6, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SRCCLKREQ2# */ PAD_NC(GPP_B7, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCIE_NVME_CLKREQ_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SRCCLKREQ4# */ PAD_NC(GPP_B9, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* EXT_PWR_GATE# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* SLP_SO_L */</span><br><span style="color: hsl(0, 100%, 40%);">-/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PLT_RST_L */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SPKR */ PAD_CFG_GPI(GPP_B14, NONE, DEEP), /* GPP_B14_STRAP */</span><br><span style="color: hsl(0, 100%, 40%);">-#if IS_ENABLED(CONFIG_ZOOMBINI_USE_SPI_TPM)</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* H1_SLAVE_SPI_CS_L */</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* H1_SLAVE_SPI_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* H1_SLAVE_SPI_MISO_R */</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* H1_SLAVE_SPI_MOSI_R */</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_CLK */ PAD_NC(GPP_B16, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI1_CS# */ PAD_CFG_NF(GPP_B19, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_FPMCU_SPI_CS_L */</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_FPMCU_SPI_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_FPMCU_SPI_MISO_R */</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_FPMCU_SPI_MOSI_R */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SML1ALERT# */ PAD_CFG_GPI(GPP_B23, NONE, DEEP), /* GPP_B23_STRAP */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SMBCLK */ PAD_NC(GPP_C0, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SMBDATA */ PAD_NC(GPP_C1, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SMBALERT# */ PAD_CFG_GPI(GPP_C2, NONE, DEEP), /* GPP_C2_STRAP */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SML0CLK */ PAD_CFG_GPI_APIC(GPP_C3, NONE, DEEP, LEVEL,</span><br><span style="color: hsl(0, 100%, 40%);">- NONE), /* PCH_SAR1_INT_L */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SML0DATA */ PAD_CFG_GPI_APIC(GPP_C4, NONE, DEEP, LEVEL,</span><br><span style="color: hsl(0, 100%, 40%);">- NONE), /* PCH_SAR0_INT_L */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SML0ALERT# */ PAD_CFG_GPI(GPP_C5, NONE, DEEP), /* GPP_C5_STRAP */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SM1CLK */ PAD_NC(GPP_C6, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SM1DATA */ PAD_NC(GPP_C7, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* UART_PCH_RX_DEBUG_TX */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* UART_PCH_TX_DEBUG_RX */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART0_RTS# */ PAD_CFG_GPO(GPP_C10, 1, DEEP), /* PP3300_TOUCH_EN */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART0_CTS# */ PAD_NC(GPP_C11, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* Only P0 boards need an internal pullup */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART1_RXD */ PAD_CFG_GPI_APIC(GPP_C12, UP_20K, DEEP, EDGE_SINGLE,</span><br><span style="color: hsl(0, 100%, 40%);">- INVERT), /* H1_PCH_INT_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART1_TXD */ PAD_NC(GPP_C13, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART1_RTS# */ PAD_CFG_GPI_APIC(GPP_C14, NONE, DEEP, LEVEL,</span><br><span style="color: hsl(0, 100%, 40%);">- NONE), /* TOUCHSCREEN_INT_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART1_CTS# */ PAD_NC(GPP_C15, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_TOUCHSCREEN_I2C0_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_TOUCHSCREEN_I2C0_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_DISPLAY_SAR1_I2C1_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_DISPLAY_SAR1_I2C1_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART2_RXD */ PAD_NC(GPP_C20, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART2_TXD */ PAD_NC(GPP_C21, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART2_RTS# */ PAD_NC(GPP_C22, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART2_CTS# */ PAD_NC(GPP_C23, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SPI1_CS# */ PAD_CFG_GPI(GPP_D0, NONE, DEEP), /* PCH_MEM_STRAP3 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SPI1_CLK */ PAD_NC(GPP_D1, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SPI1_MISO */ PAD_NC(GPP_D2, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SPI1_MOSI */ PAD_CFG_GPI(GPP_D3, NONE, DEEP), /* PCH_MEM_STRAP0 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* FASHTRIG */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), /* FCAM_MCLK */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_I2C1_SDA */ PAD_CFG_GPO(GPP_D7, 1, DEEP), /* FCAM_RST_L */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_I2C1_SCL */ PAD_CFG_GPO(GPP_D8, 1, DEEP), /* DMIC_PWR_EN */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_SPI_CS# */ PAD_NC(GPP_D9, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 0, DEEP), /* FCAM_PWR_EN */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_SPI_MISO */ PAD_NC(GPP_D11, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_SPI_MOSI */ PAD_CFG_GPI(GPP_D12, NONE, DEEP), /* GPP_D12_STRAP */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), /* ISH_UART_RX */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), /* ISH_UART_TX */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* TOUCHSCREEN_RST_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_UART0_CTS# */ PAD_CFG_GPO(GPP_D16, 1, DEEP), /* SPKR_HWRST_L */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* DB0_PCH_DMIC_CLK_R */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* DB0TX_PCHRX_DMIC_DATA */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DMIC_CLK0 */ PAD_NC(GPP_D19, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* DMIC_DATA0 */ PAD_NC(GPP_D20, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SPI1_IO2 */ PAD_CFG_GPI(GPP_D21, NONE, DEEP), /* PCH_MEM_STRAP1 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SPI1_IO3 */ PAD_CFG_GPI(GPP_D22, NONE, DEEP), /* PCH_MEM_STRAP2 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2S_MCLK */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SATAXPCI0 */ PAD_CFG_GPO(GPP_E0, 0, DEEP), /* RCAM_PWR_EN */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SATAXPCIE1 */ PAD_CFG_GPO(GPP_E1, 1, DEEP), /* RCAM_RST_L */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SATAXPCIE2 */ PAD_NC(GPP_E2, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* CPU_GP0 */ PAD_NC(GPP_E3, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* CPU_GP1 */ PAD_NC(GPP_E7, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SATALED# */ PAD_NC(GPP_E8, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* USB2_OCO# */ PAD_NC(GPP_E9, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* USB2_OC1# */ PAD_NC(GPP_E10, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* USB_C0_OC_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* USB_C1_OC_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* EC_USB_C0_HPD */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* EC_USB_C1_HPD */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPD_HPD2 */ PAD_CFG_NF(GPP_E15, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* EC_USB_C2_HPD */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* EDP_HPD */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPB_CTRLCLK */ PAD_NC(GPP_E18, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPB_CTRLDATA */ PAD_CFG_GPI(GPP_E19, NONE, DEEP), /* GPP_E19_STRAP */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPC_CTRLDATA */ PAD_CFG_GPI(GPP_E21, NONE, DEEP), /* GPP_E21_STRAP */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPD_CTRLDATA */ PAD_CFG_GPI(GPP_E23, NONE, DEEP), /* GPP_E23_STRAP */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2S2_SFRM */ PAD_CFG_GPO(GPP_F1, 0, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">- /* WWAN_RESET_1V8_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2S2_TXD */ PAD_NC(GPP_F2, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2S2_RXD */ PAD_NC(GPP_F3, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* CNV_BRI_DT_R */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* CNV_BRI_RSP */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C3_SDA */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), /* CNV_RGI_DT_R */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C3_SCL */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* CNV_RGI_RSP */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C4_SDA */ PAD_NC(GPP_F8, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C4_SCL */ PAD_NC(GPP_F9, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C5_SDA */ PAD_CFG_GPI(GPP_F10, NONE,</span><br><span style="color: hsl(0, 100%, 40%);">- DEEP), /* OPVR_MCIVR_BREAK_L */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C5_SCL */ PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), /* EMMC_CMD */</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DAT0 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DAT1 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), /* EMMC_DAT2 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), /* EMMC_DAT3 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), /* EMMC_DAT4 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), /* EMMC_DAT5 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), /* EMMC_DAT6 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), /* EMMC_DAT7 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* EMMC_RCLK */</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* EMMC_RST_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* RSVD */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_CMD */ PAD_NC(GPP_G0, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_DATA0 */ PAD_NC(GPP_G1, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_DATA1 */ PAD_NC(GPP_G2, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_DATA2 */ PAD_NC(GPP_G3, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_DATA3 */ PAD_NC(GPP_G4, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_CD# */ PAD_NC(GPP_G5, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_CLK */ PAD_NC(GPP_G6, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_WP */ PAD_NC(GPP_G7, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2S2_SCLK */ PAD_NC(GPP_H0, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2S2_SFRM */ PAD_CFG_NF(GPP_H1, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF3), /* CNV_RF_RESET_L */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2S2_TXD */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), /* WLAN_CLKREQ0 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2S2_RXD */ PAD_NC(GPP_H3, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C2_SDA */ PAD_NC(GPP_H4, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C2_SCL */ PAD_NC(GPP_H5, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C3_SDA */ PAD_CFG_NF(GPP_H6, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_AUDIO_I2C3_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C3_SCL */ PAD_CFG_NF(GPP_H7, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_AUDIO_I2C3_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_FCAM_I2C4_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_FCAM_I2C4_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C5_SDA */ PAD_CFG_NF(GPP_H10, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_RCAM_SAR0_I2C5_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C5_SCL */ PAD_CFG_NF(GPP_H11, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_RCAM_SAR0_I2C5_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* M2_SKT2_CFG0 */ PAD_CFG_GPI(GPP_H12, NONE, DEEP), /* PCH_WP_OD */</span><br><span style="color: hsl(0, 100%, 40%);">-/* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* M2_SKT2_CFG3 */ PAD_NC(GPP_H15, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPF_CTRLCLK */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DPPF_CTRLDATA */</span><br><span style="color: hsl(0, 100%, 40%);">-/* CPU_C10_GATE# */ PAD_CFG_NF(GPP_H18, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* CPU_C10_GATE_PCH_L */</span><br><span style="color: hsl(0, 100%, 40%);">-/* TIMESYNC0 */ PAD_NC(GPP_H19, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* IMGCLKOUT1 */ PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), /* RCAM_MCLK */</span><br><span style="color: hsl(0, 100%, 40%);">-/* GPP_H21 */ PAD_CFG_GPI(GPP_H21, NONE, DEEP), /* H21_STRAP */</span><br><span style="color: hsl(0, 100%, 40%);">-/* GPP_H22 */ PAD_NC(GPP_H22, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* GPP_H23 */ PAD_CFG_GPI(GPP_H23, NONE, DEEP), /* GPP_H23 */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* BATLOW_L */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ACPRESENT */ PAD_NC(GPD1, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* EC_PCH_PWR_BTN_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SLP_S3_L */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SLP_S4_L */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SLP_A# */ PAD_NC(GPD6, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* RSVD */ PAD_CFG_GPI(GPD7, NONE, DEEP), /* DPD7_Strap */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* PCH_SUSCLK */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SLP_WLAN# */ PAD_NC(GPD9, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SLP_S5# */ PAD_NC(GPD10, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* LANPHYC */ PAD_NC(GPD11, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Early pad configuration in bootblock */</span><br><span style="color: hsl(0, 100%, 40%);">-static const struct pad_config early_gpio_table[] = {</span><br><span style="color: hsl(0, 100%, 40%);">-#if IS_ENABLED(CONFIG_ZOOMBINI_USE_SPI_TPM)</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_SPI_H1_3V3_CS_L */</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_SPI_H1_3V3_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_SPI_H1_3V3_MISO */</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_SPI_H1_3V3_MOSI */</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_CLK */ PAD_NC(GPP_B16, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-/* Only P0 boards need an internal pullup */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART1_RXD */ PAD_CFG_GPI_APIC(GPP_C12, UP_20K, DEEP, EDGE_SINGLE,</span><br><span style="color: hsl(0, 100%, 40%);">- INVERT), /* H1_PCH_INT_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-const struct pad_config *variant_gpio_table(size_t *num)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- *num = ARRAY_SIZE(gpio_table);</span><br><span style="color: hsl(0, 100%, 40%);">- return gpio_table;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-const struct pad_config *variant_early_gpio_table(size_t *num)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- *num = ARRAY_SIZE(early_gpio_table);</span><br><span style="color: hsl(0, 100%, 40%);">- return early_gpio_table;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/google/zoombini/variants/meowth/include/variant/acpi/dptf.asl b/src/mainboard/google/zoombini/variants/meowth/include/variant/acpi/dptf.asl</span><br><span>deleted file mode 100644</span><br><span>index a9ec742..0000000</span><br><span>--- a/src/mainboard/google/zoombini/variants/meowth/include/variant/acpi/dptf.asl</span><br><span>+++ /dev/null</span><br><span>@@ -1,16 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2017 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <baseboard/acpi/dptf.asl></span><br><span>diff --git a/src/mainboard/google/zoombini/variants/meowth/include/variant/ec.h b/src/mainboard/google/zoombini/variants/meowth/include/variant/ec.h</span><br><span>deleted file mode 100644</span><br><span>index ef47d37..0000000</span><br><span>--- a/src/mainboard/google/zoombini/variants/meowth/include/variant/ec.h</span><br><span>+++ /dev/null</span><br><span>@@ -1,21 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2017 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef __MAINBOARD_EC_H__</span><br><span style="color: hsl(0, 100%, 40%);">-#define __MAINBOARD_EC_H__</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <baseboard/ec.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#endif /* __MAINBOARD_EC_H__ */</span><br><span>diff --git a/src/mainboard/google/zoombini/variants/meowth/include/variant/gpio.h b/src/mainboard/google/zoombini/variants/meowth/include/variant/gpio.h</span><br><span>deleted file mode 100644</span><br><span>index 136e11b..0000000</span><br><span>--- a/src/mainboard/google/zoombini/variants/meowth/include/variant/gpio.h</span><br><span>+++ /dev/null</span><br><span>@@ -1,21 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2017 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef __MAINBOARD_GPIO_H__</span><br><span style="color: hsl(0, 100%, 40%);">-#define __MAINBOARD_GPIO_H__</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <baseboard/gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#endif /* __MAINBOARD_GPIO_H__ */</span><br><span>diff --git a/src/mainboard/google/zoombini/variants/meowth/memory.c b/src/mainboard/google/zoombini/variants/meowth/memory.c</span><br><span>deleted file mode 100644</span><br><span>index 02c9ab9..0000000</span><br><span>--- a/src/mainboard/google/zoombini/variants/meowth/memory.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,92 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2017 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <baseboard/variants.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <baseboard/gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/cnl_memcfg_init.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static const struct cnl_mb_cfg meowth_lpddr4_cfg = {</span><br><span style="color: hsl(0, 100%, 40%);">- .dq_map[DDR_CH0] = {</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * CLK0 goes to package 0 - Bytes[3:0],</span><br><span style="color: hsl(0, 100%, 40%);">- * CLK1 goes to package 1 - Bytes[7:4]</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- { 0x0F, 0xF0 },</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Cmd CAA goes to Bytes[3:0],</span><br><span style="color: hsl(0, 100%, 40%);">- * Cmd CAB goes to Bytes[7:4]</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- { 0x0F, 0xF0 },</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* CTL (CS) goes to all bytes */</span><br><span style="color: hsl(0, 100%, 40%);">- { 0xFF, 0x00 },</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- .dq_map[DDR_CH1] = {</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * CLK0 goes to package 0 - Bytes[3:0],</span><br><span style="color: hsl(0, 100%, 40%);">- * CLK1 goes to package 1 - Bytes[7:4]</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- { 0x0F, 0xF0 },</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Cmd CAA goes to Bytes[3:0],</span><br><span style="color: hsl(0, 100%, 40%);">- * Cmd CAB goes to Bytes[7:4]</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- { 0x0F, 0xF0 },</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* CTL (CS) goes to all bytes */</span><br><span style="color: hsl(0, 100%, 40%);">- { 0xFF, 0x00 },</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * The dqs_map arrays map the lpddr4 pins to the SoC pins</span><br><span style="color: hsl(0, 100%, 40%);">- * for both channels.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * On Intel's memory spreadsheet, enter the following:</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * the index = dqs pin/set number on lpddr4 part</span><br><span style="color: hsl(0, 100%, 40%);">- * the value = dqs pin/set number on SoC</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * and it will translate that and display 8 values per channel.</span><br><span style="color: hsl(0, 100%, 40%);">- * Those values are copied into the dqs_map arrays below.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- .dqs_map[DDR_CH0] = { 3, 1, 2, 0, 7, 5, 6, 4 },</span><br><span style="color: hsl(0, 100%, 40%);">- .dqs_map[DDR_CH1] = { 2, 3, 1, 0, 7, 5, 6, 4 },</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Meowth uses three 100 Ohm rcomp resistors */</span><br><span style="color: hsl(0, 100%, 40%);">- .rcomp_resistor = { 100, 100, 100 },</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Meowth Rcomp target values.</span><br><span style="color: hsl(0, 100%, 40%);">- * Rcomp targets for zoombini should be</span><br><span style="color: hsl(0, 100%, 40%);">- * { 80, 40, 40, 40, 30 }, but we need to</span><br><span style="color: hsl(0, 100%, 40%);">- * nil out rcomp targets for now to avoid bug b:70896346</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- .rcomp_targets = { 0, 0, 0, 0, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Meowth is a non-interleaved design */</span><br><span style="color: hsl(0, 100%, 40%);">- .dq_pins_interleaved = 0,</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable Early Command Training */</span><br><span style="color: hsl(0, 100%, 40%);">- .ect = 1,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-const struct cnl_mb_cfg *variant_lpddr4_config(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return &meowth_lpddr4_cfg;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/google/zoombini/variants/zoombini/Makefile.inc b/src/mainboard/google/zoombini/variants/zoombini/Makefile.inc</span><br><span>deleted file mode 100644</span><br><span>index bfa1848..0000000</span><br><span>--- a/src/mainboard/google/zoombini/variants/zoombini/Makefile.inc</span><br><span>+++ /dev/null</span><br><span>@@ -1,18 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## Copyright 2018 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">-## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">-## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">-## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">-## GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-SPD_SOURCES = Hynix_H9HCNNN8KUMLHR_1GB # 0b000</span><br><span style="color: hsl(0, 100%, 40%);">-SPD_SOURCES += Micron_MT53B512M32D2_2GB # 0b001</span><br><span style="color: hsl(0, 100%, 40%);">-SPD_SOURCES += Micron_MT53B1024M32D4_4GB # 0b010</span><br><span>diff --git a/src/mainboard/google/zoombini/variants/zoombini/include/variant/acpi/dptf.asl b/src/mainboard/google/zoombini/variants/zoombini/include/variant/acpi/dptf.asl</span><br><span>deleted file mode 100644</span><br><span>index 15c46e4..0000000</span><br><span>--- a/src/mainboard/google/zoombini/variants/zoombini/include/variant/acpi/dptf.asl</span><br><span>+++ /dev/null</span><br><span>@@ -1,16 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2017 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <baseboard/acpi/dptf.asl></span><br><span>diff --git a/src/mainboard/google/zoombini/variants/zoombini/include/variant/ec.h b/src/mainboard/google/zoombini/variants/zoombini/include/variant/ec.h</span><br><span>deleted file mode 100644</span><br><span>index ef47d37..0000000</span><br><span>--- a/src/mainboard/google/zoombini/variants/zoombini/include/variant/ec.h</span><br><span>+++ /dev/null</span><br><span>@@ -1,21 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2017 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef __MAINBOARD_EC_H__</span><br><span style="color: hsl(0, 100%, 40%);">-#define __MAINBOARD_EC_H__</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <baseboard/ec.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#endif /* __MAINBOARD_EC_H__ */</span><br><span>diff --git a/src/mainboard/google/zoombini/variants/zoombini/include/variant/gpio.h b/src/mainboard/google/zoombini/variants/zoombini/include/variant/gpio.h</span><br><span>deleted file mode 100644</span><br><span>index 4f79495..0000000</span><br><span>--- a/src/mainboard/google/zoombini/variants/zoombini/include/variant/gpio.h</span><br><span>+++ /dev/null</span><br><span>@@ -1,21 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2017 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef __MAINBOARD_GPIO_H__</span><br><span style="color: hsl(0, 100%, 40%);">-#define __MAINBOARD_GPIO_H__</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <baseboard/gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#endif /* __MAINBOARD_GPIO_H__ */</span><br><span>diff --git a/util/release/genrelnotes b/util/release/genrelnotes</span><br><span>index 42848a1..0cc8b08 100755</span><br><span>--- a/util/release/genrelnotes</span><br><span>+++ b/util/release/genrelnotes</span><br><span>@@ -313,7 +313,6 @@</span><br><span> get_log_dedupe "Siemens mc_apl1" "src/mainboard/siemens/mc_apl1" "mc_apl1"</span><br><span> get_log_dedupe "Intel Apollolake" "src/soc/intel/apollolake" "apollolake\|apollo.lake"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-get_log_dedupe "Google Zoombini / Intel cannonlake_rvp" "src/mainboard/google/zoombini src/mainboard/intel/cannonlake_rvp" "zoombini\|cannonlake_rvp"</span><br><span> get_log_dedupe "Intel CannonLake" "src/soc/intel/cannonlake src/mainboard/intel/cannonlake_rvp" "cannonlake"</span><br><span> </span><br><span> get_log_dedupe "Intel Galileo" "src/mainboard/intel/galileo" "galileo"</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30094">change 30094</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30094"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: Iab2737940f07afb4f5a29ff50e6cb2a22027c51b </div>
<div style="display:none"> Gerrit-Change-Number: 30094 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Bob Moragues <moragues@chromium.org> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>