<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30064">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[WIP]amd/fam10: Implement POSTCAR stage<br><br>This patch does the following:<br>- Set up a postcar frame for the ramstage to use<br>- Implements an assembly version of the CAR tear down for the postcar stage to<br> use<br>- Gets rid of the HIGH_MEMORY for S3 resume support<br><br>TODO clean things up<br><br>Change-Id: I23dd48700777d3afeca27c8e78a48f81f7d6c589<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/cpu/amd/car/cache_as_ram.inc<br>A src/cpu/amd/car/exit_car.S<br>M src/cpu/amd/car/post_cache_as_ram.c<br>A src/cpu/amd/car/postcar.c<br>M src/cpu/amd/family_10h-family_15h/Kconfig<br>M src/cpu/amd/family_10h-family_15h/Makefile.inc<br>M src/cpu/amd/family_10h-family_15h/ram_calc.c<br>M src/include/cpu/amd/car.h<br>M src/northbridge/amd/amdfam10/Makefile.inc<br>M src/northbridge/amd/amdfam10/amdfam10.h<br>10 files changed, 195 insertions(+), 117 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/30064/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc</span><br><span>index e4c2704..2a427af 100644</span><br><span>--- a/src/cpu/amd/car/cache_as_ram.inc</span><br><span>+++ b/src/cpu/amd/car/cache_as_ram.inc</span><br><span>@@ -597,9 +597,6 @@</span><br><span> call cache_as_ram_main</span><br><span> </span><br><span> call post_cache_as_ram</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %esp</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- call cache_as_ram_new_stack</span><br><span> </span><br><span> /* We will not go back. */</span><br><span> </span><br><span>diff --git a/src/cpu/amd/car/exit_car.S b/src/cpu/amd/car/exit_car.S</span><br><span>new file mode 100644</span><br><span>index 0000000..12597e9</span><br><span>--- /dev/null</span><br><span>+++ b/src/cpu/amd/car/exit_car.S</span><br><span>@@ -0,0 +1,125 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Arthur Heymans <arthur@aheymans.xyz></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/mtrr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/cache.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/post_code.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/amd/mtrr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/amd/msr.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+.code32</span><br><span style="color: hsl(120, 100%, 40%);">+.global chipset_teardown_car</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+chipset_teardown_car:</span><br><span style="color: hsl(120, 100%, 40%);">+ pop %esp</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x30)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable cache. */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %cr0, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ orl $CR0_CacheDisable, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %eax, %cr0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x31)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ xor %eax, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ xor %edx, %edx</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $MTRR_FIX_4K_C8000, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+#if (CONFIG_DCACHE_RAM_SIZE > 0x8000)</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $MTRR_FIX_4K_C0000, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if (CONFIG_DCACHE_RAM_SIZE > 0x10000)</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $MTRR_FIX_4K_D0000, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if (CONFIG_DCACHE_RAM_SIZE > 0x18000)</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $MTRR_FIX_4K_D8000, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* disable fixed mtrr from now on,</span><br><span style="color: hsl(120, 100%, 40%);">+ * it will be enabled by ramstage again</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $SYSCFG_MSR, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ rdmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ andl $(~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn)) , %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable MTRR. */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $MTRR_DEF_TYPE_MSR, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ rdmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ andl $(~MTRR_DEF_TYPE_EN), %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable Cache */</span><br><span style="color: hsl(120, 100%, 40%);">+ mov %cr0, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ and $(~(CR0_CD | CR0_NW)), %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ mov %eax, %cr0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* INVDWBINVD = 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $HWCR_MSR, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ orl $(1 << 4), %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Fetch family */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $0x80000001, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ cpuid</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %eax, %ebx</span><br><span style="color: hsl(120, 100%, 40%);">+ andl $(0xf00000), %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ shrl $16, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ andl $(0xf00), %ebx</span><br><span style="color: hsl(120, 100%, 40%);">+ shrl $8, %ebx</span><br><span style="color: hsl(120, 100%, 40%);">+ orl %ebx, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ cmpl $0x6f, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ jl ret</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Family 15h or later */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DisSS = 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $LS_CFG_MSR, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ rdmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ andl $(~(1 << 28)), %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DisSpecTlbRld = 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $IC_CFG_MSR, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ rdmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ andl $(~(1 << 9)), %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Erratum 714: SpecNbReqDis = 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $BU_CFG2_MSR, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ rdmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ andl $(~(1 << 8)), %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DisSpecTlbRld = 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DisHwPf = 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $DC_CFG_MSR, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ rdmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ andl $(~(1 << 4)), %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ andl $(~(1 << 13)), %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x32)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Return to caller. */</span><br><span style="color: hsl(120, 100%, 40%);">+ret:</span><br><span style="color: hsl(120, 100%, 40%);">+ jmp *%esp</span><br><span>diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c</span><br><span>index e55ef40..90d9617 100644</span><br><span>--- a/src/cpu/amd/car/post_cache_as_ram.c</span><br><span>+++ b/src/cpu/amd/car/post_cache_as_ram.c</span><br><span>@@ -26,6 +26,7 @@</span><br><span> #include <cpu/amd/msr.h></span><br><span> #include <arch/acpi.h></span><br><span> #include <romstage_handoff.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbmem.h></span><br><span> </span><br><span> #include "cpu/amd/car/disable_cache_as_ram.c"</span><br><span> </span><br><span>@@ -36,76 +37,6 @@</span><br><span> #error "You need to set CONFIG_RAMTOP greater than 1M"</span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if IS_ENABLED(CONFIG_DEBUG_CAR)</span><br><span style="color: hsl(0, 100%, 40%);">-#define print_car_debug(format, arg...) printk(BIOS_DEBUG, "%s: " format, __func__, ##arg)</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">-#define print_car_debug(format, arg...)</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static size_t backup_size(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- size_t car_size = car_data_size();</span><br><span style="color: hsl(0, 100%, 40%);">- return ALIGN(car_size + 1024, 1024);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void memcpy_(void *d, const void *s, size_t len)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- print_car_debug(" Copy [%08x-%08x] to [%08x - %08x] ...",</span><br><span style="color: hsl(0, 100%, 40%);">- (uint32_t) s, (uint32_t) (s + len - 1),</span><br><span style="color: hsl(0, 100%, 40%);">- (uint32_t) d, (uint32_t) (d + len - 1));</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(d, s, len);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void memset_(void *d, int val, size_t len)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- print_car_debug(" Fill [%08x-%08x] ...",</span><br><span style="color: hsl(0, 100%, 40%);">- (uint32_t) d, (uint32_t) (d + len - 1));</span><br><span style="color: hsl(0, 100%, 40%);">- memset(d, val, len);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static int memcmp_(void *d, const void *s, size_t len)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- print_car_debug(" Compare [%08x-%08x] with [%08x - %08x] ...",</span><br><span style="color: hsl(0, 100%, 40%);">- (uint32_t) s, (uint32_t) (s + len - 1),</span><br><span style="color: hsl(0, 100%, 40%);">- (uint32_t) d, (uint32_t) (d + len - 1));</span><br><span style="color: hsl(0, 100%, 40%);">- return memcmp(d, s, len);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void prepare_romstage_ramstack(int s3resume)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- size_t backup_top = backup_size();</span><br><span style="color: hsl(0, 100%, 40%);">- print_car_debug("Prepare CAR migration and stack regions...");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (s3resume) {</span><br><span style="color: hsl(0, 100%, 40%);">- void *resume_backup_memory =</span><br><span style="color: hsl(0, 100%, 40%);">- acpi_backup_container(CONFIG_RAMBASE, HIGH_MEMORY_SAVE);</span><br><span style="color: hsl(0, 100%, 40%);">- if (resume_backup_memory)</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy_(resume_backup_memory</span><br><span style="color: hsl(0, 100%, 40%);">- + HIGH_MEMORY_SAVE - backup_top,</span><br><span style="color: hsl(0, 100%, 40%);">- (void *)(CONFIG_RAMTOP - backup_top),</span><br><span style="color: hsl(0, 100%, 40%);">- backup_top);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- memset_((void *)(CONFIG_RAMTOP - backup_top), 0, backup_top);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- print_car_debug(" Done\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void prepare_ramstage_region(int s3resume)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- size_t backup_top = backup_size();</span><br><span style="color: hsl(0, 100%, 40%);">- print_car_debug("Prepare ramstage memory region...");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (s3resume) {</span><br><span style="color: hsl(0, 100%, 40%);">- void *resume_backup_memory =</span><br><span style="color: hsl(0, 100%, 40%);">- acpi_backup_container(CONFIG_RAMBASE, HIGH_MEMORY_SAVE);</span><br><span style="color: hsl(0, 100%, 40%);">- if (resume_backup_memory)</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy_(resume_backup_memory, (void *) CONFIG_RAMBASE,</span><br><span style="color: hsl(0, 100%, 40%);">- HIGH_MEMORY_SAVE - backup_top);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- print_car_debug(" Done\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Disable Erratum 343 Workaround, see RevGuide for Fam10h, Pub#41322 Rev 3.33</span><br><span> * and RevGuide for Fam12h, Pub#44739 Rev 3.10</span><br><span> */</span><br><span>@@ -120,7 +51,37 @@</span><br><span> wrmsr(BU_CFG2_MSR, msr);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-asmlinkage void *post_cache_as_ram(void)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ROMSTAGE_RAM_STACK_SIZE 0x5000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* platform_enter_postcar() determines the stack to use after</span><br><span style="color: hsl(120, 100%, 40%);">+ * cache-as-ram is torn down as well as the MTRR settings to use,</span><br><span style="color: hsl(120, 100%, 40%);">+ * and continues execution in postcar stage. */</span><br><span style="color: hsl(120, 100%, 40%);">+static void platform_enter_postcar(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct postcar_frame pcf;</span><br><span style="color: hsl(120, 100%, 40%);">+ uintptr_t top_of_ram;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))</span><br><span style="color: hsl(120, 100%, 40%);">+ die("Unable to initialize postcar frame.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Cache the ROM as WP just below 4GiB. */</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Cache 8 MiB region below the top of ram. */</span><br><span style="color: hsl(120, 100%, 40%);">+ top_of_ram = (uintptr_t)cbmem_top();</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB,</span><br><span style="color: hsl(120, 100%, 40%);">+ MTRR_TYPE_WRBACK);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ run_postcar_phase(&pcf);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* We do not return here. */</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+asmlinkage void post_cache_as_ram(void)</span><br><span> {</span><br><span> uint32_t family = amd_fam1x_cpu_family();</span><br><span> int s3resume = 0;</span><br><span>@@ -137,8 +98,6 @@</span><br><span> </span><br><span> s3resume = acpi_is_wakeup_s3();</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- prepare_romstage_ramstack(s3resume);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> romstage_handoff_init(s3resume);</span><br><span> </span><br><span> /* from here don't store more data in CAR */</span><br><span>@@ -147,41 +106,7 @@</span><br><span> vErrata343();</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- size_t car_size = car_data_size();</span><br><span style="color: hsl(0, 100%, 40%);">- void *migrated_car = (void *)(CONFIG_RAMTOP - car_size);</span><br><span style="color: hsl(120, 100%, 40%);">+ platform_enter_postcar();</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- print_car_debug("Copying data from cache to RAM...");</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy_(migrated_car, _car_relocatable_data_start, car_size);</span><br><span style="color: hsl(0, 100%, 40%);">- print_car_debug(" Done\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- print_car_debug("Verifying data integrity in RAM...");</span><br><span style="color: hsl(0, 100%, 40%);">- if (memcmp_(migrated_car, _car_relocatable_data_start, car_size) == 0)</span><br><span style="color: hsl(0, 100%, 40%);">- print_car_debug(" Done\n");</span><br><span style="color: hsl(0, 100%, 40%);">- else</span><br><span style="color: hsl(0, 100%, 40%);">- print_car_debug(" FAILED\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* New stack grows right below migrated_car. */</span><br><span style="color: hsl(0, 100%, 40%);">- print_car_debug("Switching to use RAM as stack...");</span><br><span style="color: hsl(0, 100%, 40%);">- return migrated_car;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-asmlinkage void cache_as_ram_new_stack(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- print_car_debug("Disabling cache as RAM now\n");</span><br><span style="color: hsl(0, 100%, 40%);">- disable_cache_as_ram_real(0); // inline</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- disable_cache();</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable cached access to RAM in the range 0M to CACHE_TMP_RAMTOP */</span><br><span style="color: hsl(0, 100%, 40%);">- set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);</span><br><span style="color: hsl(0, 100%, 40%);">- enable_cache();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- prepare_ramstage_region(acpi_is_wakeup_s3());</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- set_sysinfo_in_ram(1); // So other core0 could start to train mem</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*copy and execute ramstage */</span><br><span style="color: hsl(0, 100%, 40%);">- copy_and_run();</span><br><span style="color: hsl(0, 100%, 40%);">- /* We will not return */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- print_car_debug("should not be here -\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ /* We don't return here */</span><br><span> }</span><br><span>diff --git a/src/cpu/amd/car/postcar.c b/src/cpu/amd/car/postcar.c</span><br><span>new file mode 100644</span><br><span>index 0000000..86c6c32</span><br><span>--- /dev/null</span><br><span>+++ b/src/cpu/amd/car/postcar.c</span><br><span>@@ -0,0 +1,26 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>,</span><br><span style="color: hsl(120, 100%, 40%);">+ * Raptor Engineering</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2012 Google LLC</span><br><span style="color: hsl(120, 100%, 40%);">+ * 2005.6 by yhlu</span><br><span style="color: hsl(120, 100%, 40%);">+ * 2006.3 yhlu add copy data from CAR to ram</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/cpu.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/amd/amdfam10/amdfam10.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void late_car_teardown(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ set_sysinfo_in_ram(1);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig</span><br><span>index 8e90247..8d50a46 100644</span><br><span>--- a/src/cpu/amd/family_10h-family_15h/Kconfig</span><br><span>+++ b/src/cpu/amd/family_10h-family_15h/Kconfig</span><br><span>@@ -11,7 +11,8 @@</span><br><span> select HAVE_MONOTONIC_TIMER</span><br><span> select SUPPORT_CPU_UCODE_IN_CBFS</span><br><span> select CPU_MICROCODE_MULTIPLE_FILES if !CPU_MICROCODE_CBFS_NONE</span><br><span style="color: hsl(0, 100%, 40%);">- select ACPI_HUGE_LOWMEM_BACKUP</span><br><span style="color: hsl(120, 100%, 40%);">+ select POSTCAR_STAGE</span><br><span style="color: hsl(120, 100%, 40%);">+ select POSTCAR_CONSOLE</span><br><span> </span><br><span> if CPU_AMD_MODEL_10XXX</span><br><span> </span><br><span>diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc</span><br><span>index 2ed76e1..c5d1fa5 100644</span><br><span>--- a/src/cpu/amd/family_10h-family_15h/Makefile.inc</span><br><span>+++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc</span><br><span>@@ -1,6 +1,9 @@</span><br><span> romstage-y += ../../x86/mtrr/earlymtrr.c</span><br><span> romstage-y += ../car/post_cache_as_ram.c</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += ../car/exit_car.S</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += ../car/postcar.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> romstage-y += init_cpus.c</span><br><span> </span><br><span> ramstage-y += model_10xxx_init.c</span><br><span>@@ -11,6 +14,7 @@</span><br><span> ramstage-y += tsc_freq.c</span><br><span> romstage-y += ram_calc.c</span><br><span> ramstage-y += ram_calc.c</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += ram_calc.c</span><br><span> ramstage-y += monotonic_timer.c</span><br><span> ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c</span><br><span> </span><br><span>diff --git a/src/cpu/amd/family_10h-family_15h/ram_calc.c b/src/cpu/amd/family_10h-family_15h/ram_calc.c</span><br><span>index ab2cafd..db7fc40 100644</span><br><span>--- a/src/cpu/amd/family_10h-family_15h/ram_calc.c</span><br><span>+++ b/src/cpu/amd/family_10h-family_15h/ram_calc.c</span><br><span>@@ -68,7 +68,7 @@</span><br><span> if (is_fam15h()) {</span><br><span> enable_cc6 = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#ifdef __PRE_RAM__</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __SIMPLE_DEVICE__</span><br><span> if (pci_read_config32(PCI_DEV(0, 0x18, 2), 0x118) & (0x1 << 18))</span><br><span> enable_cc6 = 1;</span><br><span> #else</span><br><span>diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h</span><br><span>index 359fa6b..b71dda0 100644</span><br><span>--- a/src/include/cpu/amd/car.h</span><br><span>+++ b/src/include/cpu/amd/car.h</span><br><span>@@ -4,8 +4,7 @@</span><br><span> #include <arch/cpu.h></span><br><span> </span><br><span> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);</span><br><span style="color: hsl(0, 100%, 40%);">-asmlinkage void *post_cache_as_ram(void);</span><br><span style="color: hsl(0, 100%, 40%);">-asmlinkage void cache_as_ram_new_stack(void);</span><br><span style="color: hsl(120, 100%, 40%);">+asmlinkage void post_cache_as_ram(void);</span><br><span> </span><br><span> void disable_cache_as_ram(void);</span><br><span> </span><br><span>diff --git a/src/northbridge/amd/amdfam10/Makefile.inc b/src/northbridge/amd/amdfam10/Makefile.inc</span><br><span>index 787f444..c3705a8 100644</span><br><span>--- a/src/northbridge/amd/amdfam10/Makefile.inc</span><br><span>+++ b/src/northbridge/amd/amdfam10/Makefile.inc</span><br><span>@@ -8,6 +8,7 @@</span><br><span> # Generic ROMSTAGE stuff</span><br><span> romstage-y += reset_test.c debug.c setup_resource_map.c raminit_sysinfo_in_ram.c</span><br><span> romstage-y += raminit_amdmct.c pci.c early_ht.c amdfam10_util.c</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += raminit_sysinfo_in_ram.c</span><br><span> </span><br><span> # RAMSTAGE</span><br><span> ramstage-y += northbridge.c misc_control.c link_control.c nb_control.c</span><br><span>diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h</span><br><span>index f16ef83..c28022e 100644</span><br><span>--- a/src/northbridge/amd/amdfam10/amdfam10.h</span><br><span>+++ b/src/northbridge/amd/amdfam10/amdfam10.h</span><br><span>@@ -912,7 +912,7 @@</span><br><span> </span><br><span> #include "nums.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#ifdef __PRE_RAM__</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __SIMPLE_DEVICE__</span><br><span> #if NODE_NUMS == 64</span><br><span> #define NODE_PCI(x, fn) ((x < 32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))</span><br><span> #else</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30064">change 30064</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30064"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I23dd48700777d3afeca27c8e78a48f81f7d6c589 </div>
<div style="display:none"> Gerrit-Change-Number: 30064 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-Reviewer: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-Reviewer: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>