<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30058">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">cpu/via/nano: Implement POSTCAR stage<br><br>Use postcar frame functions to set up an environment that the relocatable<br>ramstage can use.<br><br>Untested<br><br>Change-Id: I2d792f5d9e5109956945bf6bd783d887dd7bb5db<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/cpu/via/car/cache_as_ram.inc<br>M src/cpu/via/nano/Kconfig<br>M src/cpu/via/nano/Makefile.inc<br>M src/mainboard/via/epia-m850/romstage.c<br>M src/northbridge/via/vx900/Makefile.inc<br>M src/northbridge/via/vx900/memmap.c<br>M src/northbridge/via/vx900/vx900.h<br>7 files changed, 36 insertions(+), 62 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/30058/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc</span><br><span>index b7803d8..cd27539 100644</span><br><span>--- a/src/cpu/via/car/cache_as_ram.inc</span><br><span>+++ b/src/cpu/via/car/cache_as_ram.inc</span><br><span>@@ -169,69 +169,9 @@</span><br><span> pushl %eax /* BIST */</span><br><span> call main</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * TODO: Backup stack in CACHE_AS_RAM into MMX and SSE and after we</span><br><span style="color: hsl(0, 100%, 40%);">- * get STACK up, we restore that. It is only needed if we</span><br><span style="color: hsl(0, 100%, 40%);">- * want to go back.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* We don't need CAR from now on. */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- orl $CR0_CacheDisable, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set the default memory type and enable variable MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- /* TODO: Or also enable fixed MTRRs? Bug in the code? */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_DEF_TYPE_MSR, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %edx, %edx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(MTRR_DEF_TYPE_EN), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable caching for 0..CACHE_TMP_RAMTOP. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_PHYS_BASE(0), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %edx, %edx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(0x0 | MTRR_TYPE_WRBACK), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_PHYS_MASK(0), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $0x0000000f, %edx /* AMD 40 bit 0xff */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Cache XIP_ROM area to speedup coreboot code. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_PHYS_BASE(1), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %edx, %edx</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * IMPORTANT: The following calculation _must_ be done at runtime. See</span><br><span style="color: hsl(0, 100%, 40%);">- * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $_program, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- orl $MTRR_TYPE_WRBACK, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_PHYS_MASK(1), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %edx, %edx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">- invd</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-__main:</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(POST_PREPARE_RAMSTAGE)</span><br><span style="color: hsl(0, 100%, 40%);">- cld /* Clear direction flag. */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- movl $CONFIG_RAMTOP, %esp</span><br><span style="color: hsl(0, 100%, 40%);">- movl %esp, %ebp</span><br><span style="color: hsl(0, 100%, 40%);">- call copy_and_run</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Should never see this postcode */</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(POST_DEAD_CODE)</span><br><span> </span><br><span> .Lhlt:</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(POST_DEAD_CODE)</span><br><span> hlt</span><br><span> jmp .Lhlt</span><br><span>diff --git a/src/cpu/via/nano/Kconfig b/src/cpu/via/nano/Kconfig</span><br><span>index c7e7060..b789e45 100644</span><br><span>--- a/src/cpu/via/nano/Kconfig</span><br><span>+++ b/src/cpu/via/nano/Kconfig</span><br><span>@@ -29,6 +29,8 @@</span><br><span> select MMX</span><br><span> select SSE2</span><br><span> select SUPPORT_CPU_UCODE_IN_CBFS</span><br><span style="color: hsl(120, 100%, 40%);">+ select POSTCAR_STAGE</span><br><span style="color: hsl(120, 100%, 40%);">+ select POSTCAR_CONSOLE</span><br><span> </span><br><span> config DCACHE_RAM_BASE</span><br><span> hex</span><br><span>diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc</span><br><span>index 43d0352..2a865ac 100644</span><br><span>--- a/src/cpu/via/nano/Makefile.inc</span><br><span>+++ b/src/cpu/via/nano/Makefile.inc</span><br><span>@@ -26,3 +26,5 @@</span><br><span> cpu_microcode_bins += 3rdparty/blobs/cpu/via/nano/microcode.bin</span><br><span> </span><br><span> cpu_incs-y += $(src)/cpu/via/car/cache_as_ram.inc</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += ../car/exit_car.S</span><br><span>\ No newline at end of file</span><br><span>diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c</span><br><span>index dd303b7..7709709 100644</span><br><span>--- a/src/mainboard/via/epia-m850/romstage.c</span><br><span>+++ b/src/mainboard/via/epia-m850/romstage.c</span><br><span>@@ -98,4 +98,6 @@</span><br><span> /* FIXME: See if this is needed or take this out please */</span><br><span> /* Disable Memcard and SDIO */</span><br><span> pci_mod_config8(LPC, 0x51, 0, (1 << 7) | (1 << 4));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ platform_enter_postcar();</span><br><span> }</span><br><span>diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc</span><br><span>index bbfe63b..ec9edf3 100644</span><br><span>--- a/src/northbridge/via/vx900/Makefile.inc</span><br><span>+++ b/src/northbridge/via/vx900/Makefile.inc</span><br><span>@@ -48,4 +48,6 @@</span><br><span> bootblock-y += romstrap.ld</span><br><span> bootblock-y += romstrap.S</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += memmap.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif</span><br><span>diff --git a/src/northbridge/via/vx900/memmap.c b/src/northbridge/via/vx900/memmap.c</span><br><span>index 8cc7607..82aedbf 100644</span><br><span>--- a/src/northbridge/via/vx900/memmap.c</span><br><span>+++ b/src/northbridge/via/vx900/memmap.c</span><br><span>@@ -19,6 +19,7 @@</span><br><span> </span><br><span> #include "vx900.h"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/mtrr.h></span><br><span> #include <device/pci.h></span><br><span> #include <cbmem.h></span><br><span> </span><br><span>@@ -27,6 +28,8 @@</span><br><span> #define CHROME_9_HD_MIN_FB_SIZE 8</span><br><span> #define CHROME_9_HD_MAX_FB_SIZE 512</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define ROMSTAGE_RAM_STACK_SIZE 0x5000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Helper to determine the framebuffer size */</span><br><span> void vx900_set_chrome9hd_fb_size(u32 size_mb)</span><br><span> {</span><br><span>@@ -126,3 +129,25 @@</span><br><span> </span><br><span> return (void *)((tolm - fb_size) << 20);</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void platform_enter_postcar(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct postcar_frame pcf;</span><br><span style="color: hsl(120, 100%, 40%);">+ uintptr_t top_of_ram;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))</span><br><span style="color: hsl(120, 100%, 40%);">+ die("Unable to initialize postcar frame.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Cache the ROM as WP just below 4GiB. */</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,</span><br><span style="color: hsl(120, 100%, 40%);">+ MTRR_TYPE_WRPROT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Cache at least 8 MiB below the top of ram */</span><br><span style="color: hsl(120, 100%, 40%);">+ top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB,</span><br><span style="color: hsl(120, 100%, 40%);">+ MTRR_TYPE_WRBACK);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ run_postcar_phase(&pcf);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/northbridge/via/vx900/vx900.h b/src/northbridge/via/vx900/vx900.h</span><br><span>index a2a360a..9153fe2 100644</span><br><span>--- a/src/northbridge/via/vx900/vx900.h</span><br><span>+++ b/src/northbridge/via/vx900/vx900.h</span><br><span>@@ -37,6 +37,7 @@</span><br><span> u32 vx900_get_chrome9hd_fb_size(void);</span><br><span> u8 vx900_int15_get_5f18_bl(void);</span><br><span> uint64_t get_uma_memory_base(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void platform_enter_postcar(void);</span><br><span> </span><br><span> /* We use these throughout the code. They really belong in a generic part of</span><br><span> * coreboot, but until bureaucracy gets them there, we still need them */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30058">change 30058</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30058"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I2d792f5d9e5109956945bf6bd783d887dd7bb5db </div>
<div style="display:none"> Gerrit-Change-Number: 30058 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-Reviewer: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-Reviewer: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>