<p>HAOUAS Elyes has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30045">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/southbridge: Get rid of device_t<br><br>Use of device_t is deprecated.<br><br>Change-Id: Ib4db9c263ff156966926f9576eed7e3cfb02e78a<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/southbridge/amd/sr5650/cmn.h<br>M src/southbridge/intel/lynxpoint/me_9.x.c<br>M src/southbridge/intel/lynxpoint/pch.c<br>M src/southbridge/intel/lynxpoint/usb_xhci.c<br>4 files changed, 166 insertions(+), 39 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/30045/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/amd/sr5650/cmn.h b/src/southbridge/amd/sr5650/cmn.h</span><br><span>index 859e15d..126b786 100644</span><br><span>--- a/src/southbridge/amd/sr5650/cmn.h</span><br><span>+++ b/src/southbridge/amd/sr5650/cmn.h</span><br><span>@@ -34,30 +34,54 @@</span><br><span> #define AB_INDX 0xCD8</span><br><span> #define AB_DATA (AB_INDX+4)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline u32 nb_read_index(device_t dev, u32 index_reg, u32 index)</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __SIMPLE_DEVICE__</span><br><span style="color: hsl(120, 100%, 40%);">+static inline u32 nb_read_index(pci_devfn_t dev, u32 index_reg, u32 index)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+static inline u32 nb_read_index(struct device *dev, u32 index_reg, u32 index)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> {</span><br><span> pci_write_config32(dev, index_reg, index);</span><br><span> return pci_read_config32(dev, index_reg + 0x4);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data)</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __SIMPLE_DEVICE__</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void nb_write_index(pci_devfn_t dev, u32 index_reg, u32 index,</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 data)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void nb_write_index(struct device *dev, u32 index_reg, u32 index,</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 data)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> {</span><br><span> pci_write_config32(dev, index_reg, index);</span><br><span> pci_write_config32(dev, index_reg + 0x4, data);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline u32 nbmisc_read_index(device_t nb_dev, u32 index)</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __SIMPLE_DEVICE__</span><br><span style="color: hsl(120, 100%, 40%);">+static inline u32 nbmisc_read_index(pci_devfn_t nb_dev, u32 index)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+static inline u32 nbmisc_read_index(struct device *nb_dev, u32 index)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> {</span><br><span> return nb_read_index((nb_dev), NBMISC_INDEX, (index));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline void nbmisc_write_index(device_t nb_dev, u32 index, u32 data)</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __SIMPLE_DEVICE__</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void nbmisc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void nbmisc_write_index(struct device *nb_dev, u32 index,</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 data)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> {</span><br><span> nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,</span><br><span style="color: hsl(0, 100%, 40%);">- u32 val)</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __SIMPLE_DEVICE__</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void set_nbmisc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos,</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mask, u32 val)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void set_nbmisc_enable_bits(struct device *nb_dev, u32 reg_pos,</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mask, u32 val)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> {</span><br><span> u32 reg_old, reg;</span><br><span> reg = reg_old = nbmisc_read_index(nb_dev, reg_pos);</span><br><span>@@ -68,28 +92,49 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline u32 htiu_read_index(device_t nb_dev, u32 index)</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __SIMPLE_DEVICE__</span><br><span style="color: hsl(120, 100%, 40%);">+static inline u32 htiu_read_index(pci_devfn_t nb_dev, u32 index)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+static inline u32 htiu_read_index(struct device *nb_dev, u32 index)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> {</span><br><span> return nb_read_index((nb_dev), NBHTIU_INDEX, (index));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline void htiu_write_index(device_t nb_dev, u32 index, u32 data)</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __SIMPLE_DEVICE__</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void htiu_write_index(pci_devfn_t nb_dev, u32 index, u32 data)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void htiu_write_index(struct device *nb_dev, u32 index, u32 data)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> {</span><br><span> nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline u32 nbmc_read_index(device_t nb_dev, u32 index)</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __SIMPLE_DEVICE__</span><br><span style="color: hsl(120, 100%, 40%);">+static inline u32 nbmc_read_index(pci_devfn_t nb_dev, u32 index)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+static inline u32 nbmc_read_index(struct device *nb_dev, u32 index)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> {</span><br><span> return nb_read_index((nb_dev), NBMC_INDEX, (index));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline void nbmc_write_index(device_t nb_dev, u32 index, u32 data)</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __SIMPLE_DEVICE__</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void nbmc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void nbmc_write_index(struct device *nb_dev, u32 index, u32 data)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> {</span><br><span> nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,</span><br><span style="color: hsl(0, 100%, 40%);">- u32 val)</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __SIMPLE_DEVICE__</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void set_htiu_enable_bits(pci_devfn_t nb_dev, u32 reg_pos,</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mask, u32 val)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void set_htiu_enable_bits(struct device *nb_dev, u32 reg_pos,</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mask, u32 val)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> {</span><br><span> u32 reg_old, reg;</span><br><span> reg = reg_old = htiu_read_index(nb_dev, reg_pos);</span><br><span>@@ -100,8 +145,13 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,</span><br><span style="color: hsl(0, 100%, 40%);">- u32 val)</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __SIMPLE_DEVICE__</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos,</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mask, u32 val)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void set_nbcfg_enable_bits(struct device *nb_dev, u32 reg_pos,</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mask, u32 val)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> {</span><br><span> u32 reg_old, reg;</span><br><span> reg = reg_old = pci_read_config32(nb_dev, reg_pos);</span><br><span>@@ -112,8 +162,13 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask,</span><br><span style="color: hsl(0, 100%, 40%);">- u8 val)</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __SIMPLE_DEVICE__</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void set_nbcfg_enable_bits_8(pci_devfn_t nb_dev, u32 reg_pos,</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 mask, u8 val)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void set_nbcfg_enable_bits_8(struct device *nb_dev, u32 reg_pos,</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 mask, u8 val)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> {</span><br><span> u8 reg_old, reg;</span><br><span> reg = reg_old = pci_read_config8(nb_dev, reg_pos);</span><br><span>@@ -124,8 +179,13 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,</span><br><span style="color: hsl(0, 100%, 40%);">- u32 val)</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __SIMPLE_DEVICE__</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void set_nbmc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos,</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mask, u32 val)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void set_nbmc_enable_bits(struct device *nb_dev, u32 reg_pos,</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mask, u32 val)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> {</span><br><span> u32 reg_old, reg;</span><br><span> reg = reg_old = nbmc_read_index(nb_dev, reg_pos);</span><br><span>@@ -136,7 +196,13 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val)</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __SIMPLE_DEVICE__</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void set_pcie_enable_bits(pci_devfn_t dev, u32 reg_pos, u32 mask,</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 val)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void set_pcie_enable_bits(struct device *dev, u32 reg_pos,</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mask, u32 val)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> {</span><br><span> u32 reg_old, reg;</span><br><span> reg = reg_old = nb_read_index(dev, NBPCIE_INDEX, reg_pos);</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c</span><br><span>index 574a830..e31f2e8 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/me_9.x.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/me_9.x.c</span><br><span>@@ -52,12 +52,16 @@</span><br><span> [ME_DISABLE_BIOS_PATH] = "Disable",</span><br><span> [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update",</span><br><span> };</span><br><span style="color: hsl(0, 100%, 40%);">-static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev);</span><br><span style="color: hsl(120, 100%, 40%);">+static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev);</span><br><span> #endif</span><br><span> </span><br><span> /* MMIO base address for MEI interface */</span><br><span> static u32 *mei_base_address;</span><br><span style="color: hsl(0, 100%, 40%);">-void intel_me_mbp_clear(device_t dev);</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __SIMPLE_DEVICE__</span><br><span style="color: hsl(120, 100%, 40%);">+void intel_me_mbp_clear(pci_devfn_t dev);</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+void intel_me_mbp_clear(struct device *dev);</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> </span><br><span> #if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)</span><br><span> static void mei_dump(void *ptr, int dword, int offset, const char *type)</span><br><span>@@ -112,7 +116,11 @@</span><br><span> mei_dump(ptr, dword, offset, "WRITE");</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset)</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __SIMPLE_DEVICE__</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void pci_read_dword_ptr(pci_devfn_t dev, void *ptr, int offset)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> {</span><br><span> u32 dword = pci_read_config32(dev, offset);</span><br><span> memcpy(ptr, &dword, sizeof(dword));</span><br><span>@@ -413,7 +421,11 @@</span><br><span> * mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read</span><br><span> * state machine on the BIOS end doesn't match the ME's state machine.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static void intel_me_mbp_give_up(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __SIMPLE_DEVICE__</span><br><span style="color: hsl(120, 100%, 40%);">+static void intel_me_mbp_give_up(pci_devfn_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+static void intel_me_mbp_give_up(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> {</span><br><span> struct mei_csr csr;</span><br><span> </span><br><span>@@ -429,7 +441,11 @@</span><br><span> * mbp clear routine. This will wait for the ME to indicate that</span><br><span> * the MBP has been read and cleared.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-void intel_me_mbp_clear(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __SIMPLE_DEVICE__</span><br><span style="color: hsl(120, 100%, 40%);">+void intel_me_mbp_clear(pci_devfn_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+void intel_me_mbp_clear(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> {</span><br><span> int count;</span><br><span> struct me_hfs2 hfs2;</span><br><span>@@ -657,7 +673,11 @@</span><br><span> }</span><br><span> </span><br><span> /* Determine the path that we should take based on ME status */</span><br><span style="color: hsl(0, 100%, 40%);">-static me_bios_path intel_me_path(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __SIMPLE_DEVICE__</span><br><span style="color: hsl(120, 100%, 40%);">+static me_bios_path intel_me_path(pci_devfn_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+static me_bios_path intel_me_path(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> {</span><br><span> me_bios_path path = ME_DISABLE_BIOS_PATH;</span><br><span> struct me_hfs hfs;</span><br><span>@@ -727,7 +747,11 @@</span><br><span> }</span><br><span> </span><br><span> /* Prepare ME for MEI messages */</span><br><span style="color: hsl(0, 100%, 40%);">-static int intel_mei_setup(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __SIMPLE_DEVICE__</span><br><span style="color: hsl(120, 100%, 40%);">+static int intel_mei_setup(pci_devfn_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+static int intel_mei_setup(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> {</span><br><span> struct resource *res;</span><br><span> struct mei_csr host;</span><br><span>@@ -757,7 +781,11 @@</span><br><span> }</span><br><span> </span><br><span> /* Read the Extend register hash of ME firmware */</span><br><span style="color: hsl(0, 100%, 40%);">-static int intel_me_extend_valid(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __SIMPLE_DEVICE__</span><br><span style="color: hsl(120, 100%, 40%);">+static int intel_me_extend_valid(pci_devfn_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+static int intel_me_extend_valid(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> {</span><br><span> struct me_heres status;</span><br><span> u32 extend[8] = {0};</span><br><span>@@ -804,7 +832,11 @@</span><br><span> }</span><br><span> </span><br><span> /* Check whether ME is present and do basic init */</span><br><span style="color: hsl(0, 100%, 40%);">-static void intel_me_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __SIMPLE_DEVICE__</span><br><span style="color: hsl(120, 100%, 40%);">+static void intel_me_init(pci_devfn_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+static void intel_me_init(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> {</span><br><span> struct southbridge_intel_lynxpoint_config *config = dev->chip_info;</span><br><span> me_bios_path path = intel_me_path(dev);</span><br><span>@@ -857,7 +889,13 @@</span><br><span> */</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __SIMPLE_DEVICE__</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_subsystem(pci_devfn_t dev, unsigned int vendor,</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned int device)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_subsystem(struct device *dev, unsigned int vendor,</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned int device)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> {</span><br><span> if (!vendor || !device) {</span><br><span> pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>@@ -872,7 +910,11 @@</span><br><span> .set_subsystem = set_subsystem,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void intel_me_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __SIMPLE_DEVICE__</span><br><span style="color: hsl(120, 100%, 40%);">+static void intel_me_enable(pci_devfn_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+static void intel_me_enable(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> {</span><br><span> /* Avoid talking to the device in S3 path */</span><br><span> if (acpi_is_wakeup_s3()) {</span><br><span>@@ -939,7 +981,11 @@</span><br><span> * mbp seems to be following its own flow, let's retrieve it in a dedicated</span><br><span> * function.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __SIMPLE_DEVICE__</span><br><span style="color: hsl(120, 100%, 40%);">+static int intel_me_read_mbp(me_bios_payload *mbp_data, pci_devfn_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> {</span><br><span> mbp_header mbp_hdr;</span><br><span> u32 me2host_pending;</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c</span><br><span>index cb01de7..6596aa2 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/pch.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/pch.c</span><br><span>@@ -23,14 +23,17 @@</span><br><span> #include <device/pci_def.h></span><br><span> #include "pch.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static device_t pch_get_lpc_device(void)</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __SIMPLE_DEVICE__</span><br><span style="color: hsl(120, 100%, 40%);">+static pci_devfn_t pch_get_lpc_device(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-#ifdef __SMM__</span><br><span> return PCI_DEV(0, 0x1f, 0);</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">- return dev_find_slot(0, PCI_DEVFN(0x1f, 0));</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+static struct device *pch_get_lpc_device(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return dev_find_slot(0, PCI_DEVFN(0x1f, 0));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> </span><br><span> int pch_silicon_revision(void)</span><br><span> {</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c</span><br><span>index 186e3f9..03341da 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/usb_xhci.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/usb_xhci.c</span><br><span>@@ -23,7 +23,11 @@</span><br><span> </span><br><span> typedef struct southbridge_intel_lynxpoint_config config_t;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static u8 *usb_xhci_mem_base(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __SIMPLE_DEVICE__</span><br><span style="color: hsl(120, 100%, 40%);">+static u8 *usb_xhci_mem_base(pci_devfn_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+static u8 *usb_xhci_mem_base(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> {</span><br><span> u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);</span><br><span> </span><br><span>@@ -34,7 +38,11 @@</span><br><span> return (u8 *)(mem_base & ~0xf);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int usb_xhci_port_count_usb3(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __SIMPLE_DEVICE__</span><br><span style="color: hsl(120, 100%, 40%);">+static int usb_xhci_port_count_usb3(pci_devfn_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+static int usb_xhci_port_count_usb3(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> {</span><br><span> if (pch_is_lp()) {</span><br><span> /* LynxPoint-LP has 4 SS ports */</span><br><span>@@ -81,7 +89,11 @@</span><br><span> * b) Poll for warm reset complete</span><br><span> * c) Write 1 to port change status bits</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static void usb_xhci_reset_usb3(device_t dev, int all)</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __SIMPLE_DEVICE__</span><br><span style="color: hsl(120, 100%, 40%);">+static void usb_xhci_reset_usb3(pci_devfn_t dev, int all)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+static void usb_xhci_reset_usb3(struct device *dev, int all)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> {</span><br><span> u32 status, port_disabled;</span><br><span> int timeout, port;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30045">change 30045</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30045"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: Ib4db9c263ff156966926f9576eed7e3cfb02e78a </div>
<div style="display:none"> Gerrit-Change-Number: 30045 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: HAOUAS Elyes <ehaouas@noos.fr> </div>
<div style="display:none"> Gerrit-Reviewer: HAOUAS Elyes <ehaouas@noos.fr> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>