<p>Duncan Laurie has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30062">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/sarien: Update GPIOs for next build<br><br>Update the GPIOs for the next board build. Mostly minor changes but<br>the polarity change on GPP_E8/RECOVERY on sarien will result in it<br>booting to recovery every time unless using new hardware.<br><br>For this reason the recovery mode GPIO that is passed to vboot is<br>commented out for sarien. It is only used for testing and currently<br>it is useful to have an image that works on both board versions.<br><br>Change-Id: I32d84f3010cb4d3968370a03f7e191b1710a50e8<br>Signed-off-by: Duncan Laurie <dlaurie@google.com><br>---<br>M src/mainboard/google/sarien/variants/arcada/gpio.c<br>M src/mainboard/google/sarien/variants/sarien/gpio.c<br>2 files changed, 40 insertions(+), 27 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/30062/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c</span><br><span>index 0ffd029..a29fd06 100644</span><br><span>--- a/src/mainboard/google/sarien/variants/arcada/gpio.c</span><br><span>+++ b/src/mainboard/google/sarien/variants/arcada/gpio.c</span><br><span>@@ -30,18 +30,23 @@</span><br><span> /* ESPI_CLK */</span><br><span> /* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE),</span><br><span> /* PME# */ PAD_NC(GPP_A11, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* BM_BUSY# */ PAD_NC(GPP_A12, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ISH_LID_CL#_TAB */</span><br><span style="color: hsl(120, 100%, 40%);">+/* BM_BUSY# */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),</span><br><span> /* SUSWARN# */ PAD_NC(GPP_A13, NONE),</span><br><span> /* ESPI_RESET# */</span><br><span> /* SUSACK# */ PAD_NC(GPP_A15, NONE),</span><br><span> /* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE),</span><br><span> /* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_GP0 */ PAD_NC(GPP_A18, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_GP1 */ PAD_NC(GPP_A19, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ISH_ACC1_INT# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ISH_ACC2_INT# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),</span><br><span> /* ISH_GP2 */ PAD_NC(GPP_A20, NONE),</span><br><span> /* ISH_GP3 */ PAD_NC(GPP_A21, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_GP4 */ PAD_NC(GPP_A22, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_GP5 */ PAD_NC(GPP_A23, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ISH_NB_MODE */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP4 */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ISH_LID_CL#_NB */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP5 */ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),</span><br><span> </span><br><span> /* CORE_VID0 */</span><br><span> /* CORE_VID1 */</span><br><span>@@ -49,12 +54,17 @@</span><br><span> /* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST,</span><br><span> EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */</span><br><span> /* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* LAN_CLKREQ_CPU_N */</span><br><span> /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CARD_CLKREQ_CPU_N */</span><br><span> /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* WLAN_CLKREQ_CPU_N */</span><br><span> /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* WWAN_CLKREQ_CPU_N */</span><br><span> /* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SSD_CKLREQ_CPU_N */</span><br><span> /* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), /* TBT_CLKREQ_CPU_N (nostuff) */</span><br><span> /* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */</span><br><span> /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),</span><br><span> /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),</span><br><span>@@ -63,7 +73,7 @@</span><br><span> /* GSPI0_CLK */ PAD_CFG_GPI(GPP_B16, NONE, DEEP), /* ONE_DIMM# */</span><br><span> /* GSPI0_MISO */ PAD_CFG_GPI(GPP_B17, NONE, DEEP), /* RTC_DET# */</span><br><span> /* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */</span><br><span> /* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */</span><br><span> /* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */</span><br><span> /* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE),</span><br><span>@@ -112,8 +122,10 @@</span><br><span> /* ISH_SPI_CLK */ PAD_NC(GPP_D10, NONE),</span><br><span> /* ISH_SPI_MISO */ PAD_CFG_GPI(GPP_D11, NONE, DEEP), /* TBT_DET# */</span><br><span> /* ISH_SPI_MOSI */ PAD_NC(GPP_D12, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ISH_CPU_UART0_RX */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ISH_CPU_UART0_TX */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),</span><br><span> /* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */</span><br><span> /* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE),</span><br><span> /* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */</span><br><span>@@ -144,10 +156,10 @@</span><br><span> /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DP_HPD_CPU */</span><br><span> /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DP2_HPD_CPU */</span><br><span> /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* FFS_INT2 (nostuff) */</span><br><span> /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* HDMI_SCL_CPU */</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* HDMI_SDA_CPU */</span><br><span> /* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE),</span><br><span> /* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE),</span><br><span> /* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE),</span><br><span>@@ -179,9 +191,9 @@</span><br><span> /* A4WP_PRESENT */ PAD_NC(GPP_F23, NONE),</span><br><span> </span><br><span> /* SD_CMD */ PAD_CFG_GPI(GPP_G0, NONE, DEEP), /* CAM_MIC_CBL_DET# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_DATA0 */ PAD_NC(GPP_G1, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), /* ANT_CONFIG (nostuff) */</span><br><span> /* SD_DATA1 */ PAD_NC(GPP_G2, NONE), /* TBT_CIO_PLUG_EVT# (nostuff) */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), /* T383 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA2 */ PAD_NC(GPP_G3, NONE),</span><br><span> /* SD_DATA3 */ PAD_CFG_GPI(GPP_G4, NONE, DEEP), /* CTLESS_DET# */</span><br><span> /* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, DEEP), /* HOST_SD_WP# */</span><br><span> /* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, DEEP), /* AUD_PWR_EN */</span><br><span>diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c</span><br><span>index a41d940..38d21c8 100644</span><br><span>--- a/src/mainboard/google/sarien/variants/sarien/gpio.c</span><br><span>+++ b/src/mainboard/google/sarien/variants/sarien/gpio.c</span><br><span>@@ -49,11 +49,11 @@</span><br><span> /* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST,</span><br><span> EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */</span><br><span> /* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* CLKREQ_PCIE#0 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* CLKREQ_PCIE#1 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* CLKREQ_PCIE#2 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* CLKREQ_PCIE#3 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* CLKREQ_PCIE#4 */</span><br><span> /* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE),</span><br><span> /* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */</span><br><span> /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),</span><br><span>@@ -63,8 +63,7 @@</span><br><span> /* GSPI0_CLK */ PAD_NC(GPP_B16, NONE),</span><br><span> /* GSPI0_MISO */ PAD_NC(GPP_B17, NONE),</span><br><span> /* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI1_CS# */ PAD_CFG_GPI_APIC(GPP_B19, NONE, PLTRST,</span><br><span style="color: hsl(0, 100%, 40%);">- EDGE_SINGLE, INVERT), /* HDD_FALL_INT */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */</span><br><span> /* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */</span><br><span> /* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */</span><br><span> /* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE),</span><br><span>@@ -101,7 +100,7 @@</span><br><span> EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */</span><br><span> /* SPI1_CLK */ PAD_NC(GPP_D1, NONE),</span><br><span> /* SPI1_MISO */ PAD_NC(GPP_D2, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI1_MOSI */ PAD_CFG_GPI(GPP_D3, NONE, DEEP), /* RTC_DET# */</span><br><span> /* FASHTRIG */ PAD_NC(GPP_D4, NONE),</span><br><span> /* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE),</span><br><span> /* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE),</span><br><span>@@ -135,7 +134,7 @@</span><br><span> /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* M3042_DEVSLP */</span><br><span> /* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* M2280_DEVSLP */</span><br><span> /* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* TOUCH_SCREEN_PD# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */</span><br><span> /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC0# */</span><br><span> /* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_OC1# */</span><br><span> /* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB_OC2# */</span><br><span>@@ -143,8 +142,7 @@</span><br><span> /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* HDMI_DP1_HPD */</span><br><span> /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* CPU_DP2_HPD */</span><br><span> /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPE_HPD3 */ PAD_CFG_GPI_APIC(GPP_E16, NONE, PLTRST,</span><br><span style="color: hsl(0, 100%, 40%);">- EDGE_SINGLE, INVERT), /* FFS_INT2 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* FFS_INT2 (nostuff) */</span><br><span> /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),</span><br><span> /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),</span><br><span> /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),</span><br><span>@@ -237,7 +235,7 @@</span><br><span> /* RESET# need to stay low before FULL_CARD_POWER_OFF assert */</span><br><span> /* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */</span><br><span> /* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */</span><br><span> /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */</span><br><span> };</span><br><span> </span><br><span>@@ -254,7 +252,10 @@</span><br><span> }</span><br><span> </span><br><span> static const struct cros_gpio cros_gpios[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- CROS_GPIO_REC_AH(GPP_E8, CROS_GPIO_DEVICE_NAME),</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * TODO: re-enable recovery mode when boards are updated:</span><br><span style="color: hsl(120, 100%, 40%);">+ * CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME),</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span> CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME),</span><br><span> };</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30062">change 30062</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30062"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I32d84f3010cb4d3968370a03f7e191b1710a50e8 </div>
<div style="display:none"> Gerrit-Change-Number: 30062 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Duncan Laurie <dlaurie@chromium.org> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>