<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30039">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/google/kahlee: Add romstage GPIO initialization<br><br>Move the backlight initialization from bootblock to romstage<br><br>BUG=b:120436919<br>TEST=Careena backlight is enabled<br><br>Change-Id: Ia4993b993d37afaf9e23d6f3316ba91053732f1d<br>Signed-off-by: Martin Roth <martinroth@chromium.org><br>---<br>M src/mainboard/google/kahlee/romstage.c<br>M src/mainboard/google/kahlee/variants/baseboard/gpio.c<br>M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h<br>3 files changed, 20 insertions(+), 3 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/30039/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/kahlee/romstage.c b/src/mainboard/google/kahlee/romstage.c</span><br><span>index 5ec5c25..32f8356 100644</span><br><span>--- a/src/mainboard/google/kahlee/romstage.c</span><br><span>+++ b/src/mainboard/google/kahlee/romstage.c</span><br><span>@@ -15,6 +15,7 @@</span><br><span> </span><br><span> #include <amdblocks/dimm_spd.h></span><br><span> #include <baseboard/variants.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span> #include <soc/romstage.h></span><br><span> </span><br><span> int mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len)</span><br><span>@@ -29,5 +30,11 @@</span><br><span> </span><br><span> void mainboard_romstage_entry(int s3_resume)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+  size_t num_gpios;</span><br><span style="color: hsl(120, 100%, 40%);">+     const struct soc_amd_gpio *gpios;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+   gpios = variant_romstage_gpio_table(&num_gpios);</span><br><span style="color: hsl(120, 100%, 40%);">+  sb_program_gpios(gpios, num_gpios);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>        variant_romstage_entry(s3_resume);</span><br><span> }</span><br><span>diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c</span><br><span>index 7922ea5..e9ae28c 100644</span><br><span>--- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c</span><br><span>+++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c</span><br><span>@@ -77,9 +77,6 @@</span><br><span>         /* GPIO_132 - CONFIG_STRAP4 */</span><br><span>       PAD_GPI(GPIO_132, PULL_NONE),</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-       /* GPIO_133 - APU_EDP_BKLTEN_L (backlight - Active LOW) */</span><br><span style="color: hsl(0, 100%, 40%);">-      PAD_GPO(GPIO_133, HIGH),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span>     /* GPIO_136 - UART_PCH_RX_DEBUG_TX */</span><br><span>        PAD_NF(GPIO_136, UART0_RXD, PULL_NONE),</span><br><span> </span><br><span>@@ -93,6 +90,11 @@</span><br><span>     PAD_GPI(GPIO_142, PULL_NONE),</span><br><span> };</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static const struct soc_amd_gpio gpio_set_stage_rom[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+    /* GPIO_133 - APU_EDP_BKLTEN_L (backlight - Active LOW) */</span><br><span style="color: hsl(120, 100%, 40%);">+    PAD_GPO(GPIO_133, HIGH),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static const struct soc_amd_gpio gpio_set_stage_ram[] = {</span><br><span>  /* GPIO_0 - EC_PCH_PWR_BTN_ODL */</span><br><span>    PAD_NF(GPIO_0, PWR_BTN_L, PULL_UP),</span><br><span>@@ -259,6 +261,13 @@</span><br><span> }</span><br><span> </span><br><span> const __weak</span><br><span style="color: hsl(120, 100%, 40%);">+struct soc_amd_gpio *variant_romstage_gpio_table(size_t *size)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+        *size = ARRAY_SIZE(gpio_set_stage_rom);</span><br><span style="color: hsl(120, 100%, 40%);">+       return gpio_set_stage_rom;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const __weak</span><br><span> struct soc_amd_gpio *variant_gpio_table(size_t *size)</span><br><span> {</span><br><span>  *size = ARRAY_SIZE(gpio_set_stage_ram);</span><br><span>diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h</span><br><span>index 6e89105..da65bd8 100644</span><br><span>--- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h</span><br><span>+++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h</span><br><span>@@ -28,6 +28,7 @@</span><br><span> int variant_get_xhci_oc_map(uint16_t *usb_oc_map);</span><br><span> int variant_get_ehci_oc_map(uint16_t *usb_oc_map);</span><br><span> const struct soc_amd_gpio *variant_early_gpio_table(size_t *size);</span><br><span style="color: hsl(120, 100%, 40%);">+const struct soc_amd_gpio *variant_romstage_gpio_table(size_t *size);</span><br><span> const struct soc_amd_gpio *variant_gpio_table(size_t *size);</span><br><span> void variant_romstage_entry(int s3_resume);</span><br><span> #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30039">change 30039</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30039"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: Ia4993b993d37afaf9e23d6f3316ba91053732f1d </div>
<div style="display:none"> Gerrit-Change-Number: 30039 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>