<p>Duncan Laurie <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/c/coreboot/+/29762">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Furquan Shaikh: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/sarien: Enable DPTF<br><br>Enable DPTF support for sarien/arcada boards. This is currently<br>using placeholder values that are identical that will be updated<br>after thermal tuning is done.<br><br>Change-Id: I7d51c3b38068fc25927c8dafc0bd9069b29d77f5<br>Signed-off-by: Duncan Laurie <dlaurie@google.com><br>Reviewed-on: https://review.coreboot.org/c/29762<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Furquan Shaikh <furquan@google.com><br>---<br>M src/mainboard/google/sarien/dsdt.asl<br>M src/mainboard/google/sarien/variants/arcada/devicetree.cb<br>A src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl<br>M src/mainboard/google/sarien/variants/arcada/include/variant/ec.h<br>M src/mainboard/google/sarien/variants/sarien/devicetree.cb<br>A src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl<br>M src/mainboard/google/sarien/variants/sarien/include/variant/ec.h<br>7 files changed, 137 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl</span><br><span>index bed06fe..7f46e4f 100644</span><br><span>--- a/src/mainboard/google/sarien/dsdt.asl</span><br><span>+++ b/src/mainboard/google/sarien/dsdt.asl</span><br><span>@@ -64,4 +64,15 @@</span><br><span> #include <ec/google/wilco/acpi/ec.asl></span><br><span> }</span><br><span> #endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Dynamic Platform Thermal Framework */</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_SB)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Per board variant specific definitions. */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <variant/acpi/dptf.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ /* Include soc specific DPTF changes */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/cannonlake/acpi/dptf.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ /* Include common dptf ASL files */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/common/acpi/dptf/dptf.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> }</span><br><span>diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb</span><br><span>index ee1cca0..4bd2d90 100644</span><br><span>--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb</span><br><span>+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb</span><br><span>@@ -30,6 +30,7 @@</span><br><span> </span><br><span> register "speed_shift_enable" = "1"</span><br><span> register "s0ix_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "dptf_enable" = "1"</span><br><span> </span><br><span> # Intel Common SoC Config</span><br><span> register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C</span><br><span>diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..2d35878</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl</span><br><span>@@ -0,0 +1,59 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Google LLC</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_CPU_PASSIVE 80</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_CPU_CRITICAL 100</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_SENSOR_ID 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_SENSOR_NAME "Thermal 1"</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_PASSIVE 55</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_CRITICAL 80</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_SENSOR_ID 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_SENSOR_NAME "Thermal 2"</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_PASSIVE 55</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_CRITICAL 80</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#undef DPTF_ENABLE_FAN_CONTROL</span><br><span style="color: hsl(120, 100%, 40%);">+#undef DPTF_ENABLE_CHARGER</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Name (DTRT, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CPU Throttle Effect on CPU */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CPU Effect on Board */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Name (MPPC, Package ()</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x2, /* Revision */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { /* Power Limit 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 3000, /* PowerLimitMinimum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 15000, /* PowerLimitMaximum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 28000, /* TimeWindowMinimum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 32000, /* TimeWindowMaximum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 100 /* StepSize */</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { /* Power Limit 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 15000, /* PowerLimitMinimum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 44000, /* PowerLimitMaximum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 28000, /* TimeWindowMinimum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 32000, /* TimeWindowMaximum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 100 /* StepSize */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span>diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/ec.h b/src/mainboard/google/sarien/variants/arcada/include/variant/ec.h</span><br><span>index cb73092..01a17b5 100644</span><br><span>--- a/src/mainboard/google/sarien/variants/arcada/include/variant/ec.h</span><br><span>+++ b/src/mainboard/google/sarien/variants/arcada/include/variant/ec.h</span><br><span>@@ -28,4 +28,7 @@</span><br><span> /* Enable PS/2 keyboard */</span><br><span> #define SIO_EC_ENABLE_PS2K</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* Enable DPTF */</span><br><span style="color: hsl(120, 100%, 40%);">+#define EC_ENABLE_DPTF</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #endif</span><br><span>diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb</span><br><span>index b33c923..66f1711 100644</span><br><span>--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb</span><br><span>+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb</span><br><span>@@ -30,6 +30,7 @@</span><br><span> </span><br><span> register "speed_shift_enable" = "1"</span><br><span> register "s0ix_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "dptf_enable" = "1"</span><br><span> </span><br><span> # Intel Common SoC Config</span><br><span> register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C</span><br><span>diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..2d35878</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl</span><br><span>@@ -0,0 +1,59 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Google LLC</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_CPU_PASSIVE 80</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_CPU_CRITICAL 100</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_SENSOR_ID 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_SENSOR_NAME "Thermal 1"</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_PASSIVE 55</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_CRITICAL 80</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_SENSOR_ID 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_SENSOR_NAME "Thermal 2"</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_PASSIVE 55</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_CRITICAL 80</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#undef DPTF_ENABLE_FAN_CONTROL</span><br><span style="color: hsl(120, 100%, 40%);">+#undef DPTF_ENABLE_CHARGER</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Name (DTRT, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CPU Throttle Effect on CPU */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CPU Effect on Board */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Name (MPPC, Package ()</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x2, /* Revision */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { /* Power Limit 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 3000, /* PowerLimitMinimum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 15000, /* PowerLimitMaximum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 28000, /* TimeWindowMinimum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 32000, /* TimeWindowMaximum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 100 /* StepSize */</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { /* Power Limit 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 15000, /* PowerLimitMinimum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 44000, /* PowerLimitMaximum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 28000, /* TimeWindowMinimum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 32000, /* TimeWindowMaximum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 100 /* StepSize */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span>diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/ec.h b/src/mainboard/google/sarien/variants/sarien/include/variant/ec.h</span><br><span>index cb73092..01a17b5 100644</span><br><span>--- a/src/mainboard/google/sarien/variants/sarien/include/variant/ec.h</span><br><span>+++ b/src/mainboard/google/sarien/variants/sarien/include/variant/ec.h</span><br><span>@@ -28,4 +28,7 @@</span><br><span> /* Enable PS/2 keyboard */</span><br><span> #define SIO_EC_ENABLE_PS2K</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* Enable DPTF */</span><br><span style="color: hsl(120, 100%, 40%);">+#define EC_ENABLE_DPTF</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #endif</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/29762">change 29762</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/29762"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I7d51c3b38068fc25927c8dafc0bd9069b29d77f5 </div>
<div style="display:none"> Gerrit-Change-Number: 29762 </div>
<div style="display:none"> Gerrit-PatchSet: 6 </div>
<div style="display:none"> Gerrit-Owner: Duncan Laurie <dlaurie@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: Duncan Laurie <dlaurie@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-MessageType: merged </div>