<p>Arthur Heymans <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/c/coreboot/+/29866">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Nico Huber: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/gm45: Correctly cache TSEG<br><br>Change-Id: I6a8752da9f92b90a2cb2cca5ebf28e2bc5a9c9a8<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>Reviewed-on: https://review.coreboot.org/c/29866<br>Reviewed-by: Nico Huber <nico.h@gmx.de><br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>---<br>M src/northbridge/intel/gm45/gm45.h<br>M src/northbridge/intel/gm45/northbridge.c<br>M src/northbridge/intel/gm45/ram_calc.c<br>3 files changed, 14 insertions(+), 22 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h</span><br><span>index 95863d9..5373e5e 100644</span><br><span>--- a/src/northbridge/intel/gm45/gm45.h</span><br><span>+++ b/src/northbridge/intel/gm45/gm45.h</span><br><span>@@ -434,7 +434,6 @@</span><br><span> u32 decode_igd_memory_size(u32 gms);</span><br><span> u32 decode_igd_gtt_size(u32 gsm);</span><br><span> u32 decode_tseg_size(u8 esmramc);</span><br><span style="color: hsl(0, 100%, 40%);">-uintptr_t smm_region_start(void);</span><br><span> </span><br><span> void init_iommu(void);</span><br><span> </span><br><span>diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c</span><br><span>index 0fd7fe5..a001a67 100644</span><br><span>--- a/src/northbridge/intel/gm45/northbridge.c</span><br><span>+++ b/src/northbridge/intel/gm45/northbridge.c</span><br><span>@@ -221,22 +221,6 @@</span><br><span> return NULL;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-u32 northbridge_get_tseg_base(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return (u32)smm_region_start();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-u32 northbridge_get_tseg_size(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (dev == NULL)</span><br><span style="color: hsl(0, 100%, 40%);">- die("could not find pci 00:00.0!\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- const u8 esmramc = pci_read_config8(dev, D0F0_ESMRAMC);</span><br><span style="color: hsl(0, 100%, 40%);">- return decode_tseg_size(esmramc) << 10;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> void northbridge_write_smram(u8 smram)</span><br><span> {</span><br><span> struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));</span><br><span>diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c</span><br><span>index 5af3e16..af1a46d 100644</span><br><span>--- a/src/northbridge/intel/gm45/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/gm45/ram_calc.c</span><br><span>@@ -26,6 +26,7 @@</span><br><span> #include <cpu/x86/mtrr.h></span><br><span> #include <cbmem.h></span><br><span> #include <program_loading.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/smm/gen1/smi.h></span><br><span> #include "gm45.h"</span><br><span> </span><br><span> /*</span><br><span>@@ -83,7 +84,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-uintptr_t smm_region_start(void)</span><br><span style="color: hsl(120, 100%, 40%);">+u32 northbridge_get_tseg_base(void)</span><br><span> {</span><br><span> const pci_devfn_t dev = PCI_DEV(0, 0, 0);</span><br><span> </span><br><span>@@ -106,13 +107,19 @@</span><br><span> return tor;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+u32 northbridge_get_tseg_size(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC);</span><br><span style="color: hsl(120, 100%, 40%);">+ return decode_tseg_size(esmramc) << 10;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Depending of UMA and TSEG configuration, TSEG might start at any</span><br><span> * 1 MiB alignment. As this may cause very greedy MTRR setup, push</span><br><span> * CBMEM top downwards to 4 MiB boundary.</span><br><span> */</span><br><span> void *cbmem_top(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- uintptr_t top_of_ram = ALIGN_DOWN(smm_region_start(), 4*MiB);</span><br><span style="color: hsl(120, 100%, 40%);">+ uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);</span><br><span> return (void *) top_of_ram;</span><br><span> }</span><br><span> </span><br><span>@@ -135,12 +142,14 @@</span><br><span> /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */</span><br><span> postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Cache a 8 MiB region below the top of ram and 8 MiB above top of</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Cache 8 MiB region below the top of ram and 2 MiB above top of</span><br><span> * ram to cover both cbmem as the TSEG region.</span><br><span> */</span><br><span> top_of_ram = (uintptr_t)cbmem_top();</span><br><span style="color: hsl(0, 100%, 40%);">- postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB,</span><br><span style="color: hsl(0, 100%, 40%);">- MTRR_TYPE_WRBACK);</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB,</span><br><span style="color: hsl(120, 100%, 40%);">+ MTRR_TYPE_WRBACK);</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(),</span><br><span style="color: hsl(120, 100%, 40%);">+ northbridge_get_tseg_size(), MTRR_TYPE_WRBACK);</span><br><span> </span><br><span> run_postcar_phase(&pcf);</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/29866">change 29866</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I6a8752da9f92b90a2cb2cca5ebf28e2bc5a9c9a8 </div>
<div style="display:none"> Gerrit-Change-Number: 29866 </div>
<div style="display:none"> Gerrit-PatchSet: 5 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-Reviewer: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-Reviewer: Nico Huber <nico.h@gmx.de> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-MessageType: merged </div>