<p>Patrick Georgi <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/c/coreboot/+/29977">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Nico Huber: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/common: Create a common PCH finalise implementation<br><br>The common finalise code is used by bd82x6x, Lynx Point, and Ibex Peak.<br><br>Lynx Point now benefits from being able to write-protect the flash chip.<br><br>For Lynx Point, writing the SPI OPMENU now happens in ramstage, as done<br>in bd82x6x.<br><br>Tested on an ASRock H81M-HDS (Lynx Point). When write-protection is<br>configured, flashrom reports all flash regions as read-only, and does<br>not manage to alter the contents of the flash chip.<br><br>Also tested on an ASUS P8H61-M LX (Cougar Point). Everything seems to<br>work as before.<br><br>Change-Id: I781082b1ed507b00815d1e85aec3e56ae5a4bef2<br>Signed-off-by: Tristan Corrick <tristan@corrick.kiwi><br>Reviewed-on: https://review.coreboot.org/c/29977<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Nico Huber <nico.h@gmx.de><br>---<br>M src/mainboard/lenovo/x201/smihandler.c<br>M src/mainboard/packardbell/ms2290/smihandler.c<br>M src/southbridge/intel/bd82x6x/Kconfig<br>M src/southbridge/intel/bd82x6x/Makefile.inc<br>M src/southbridge/intel/bd82x6x/pch.h<br>M src/southbridge/intel/bd82x6x/smihandler.c<br>M src/southbridge/intel/common/Kconfig<br>M src/southbridge/intel/common/Makefile.inc<br>R src/southbridge/intel/common/finalize.c<br>A src/southbridge/intel/common/finalize.h<br>M src/southbridge/intel/common/pmutil.h<br>M src/southbridge/intel/ibexpeak/Kconfig<br>M src/southbridge/intel/ibexpeak/Makefile.inc<br>M src/southbridge/intel/ibexpeak/pch.h<br>M src/southbridge/intel/lynxpoint/Kconfig<br>M src/southbridge/intel/lynxpoint/Makefile.inc<br>D src/southbridge/intel/lynxpoint/finalize.c<br>M src/southbridge/intel/lynxpoint/lpc.c<br>M src/southbridge/intel/lynxpoint/pch.h<br>M src/southbridge/intel/lynxpoint/smihandler.c<br>20 files changed, 115 insertions(+), 141 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c</span><br><span>index fbbec09..10ca4d4 100644</span><br><span>--- a/src/mainboard/lenovo/x201/smihandler.c</span><br><span>+++ b/src/mainboard/lenovo/x201/smihandler.c</span><br><span>@@ -20,6 +20,7 @@</span><br><span> #include <southbridge/intel/ibexpeak/nvs.h></span><br><span> #include <southbridge/intel/ibexpeak/pch.h></span><br><span> #include <southbridge/intel/ibexpeak/me.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/finalize.h></span><br><span> #include <northbridge/intel/nehalem/nehalem.h></span><br><span> #include <cpu/intel/model_2065x/model_2065x.h></span><br><span> #include <ec/acpi/ec.h></span><br><span>diff --git a/src/mainboard/packardbell/ms2290/smihandler.c b/src/mainboard/packardbell/ms2290/smihandler.c</span><br><span>index 926650a..e0f16f3 100644</span><br><span>--- a/src/mainboard/packardbell/ms2290/smihandler.c</span><br><span>+++ b/src/mainboard/packardbell/ms2290/smihandler.c</span><br><span>@@ -19,6 +19,7 @@</span><br><span> #include <southbridge/intel/ibexpeak/nvs.h></span><br><span> #include <southbridge/intel/ibexpeak/pch.h></span><br><span> #include <southbridge/intel/ibexpeak/me.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/finalize.h></span><br><span> #include <northbridge/intel/nehalem/nehalem.h></span><br><span> #include <cpu/intel/model_2065x/model_2065x.h></span><br><span> #include <ec/acpi/ec.h></span><br><span>diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig</span><br><span>index d906ea7..1396a63 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/Kconfig</span><br><span>+++ b/src/southbridge/intel/bd82x6x/Kconfig</span><br><span>@@ -25,6 +25,7 @@</span><br><span> def_bool y</span><br><span> select ACPI_INTEL_HARDWARE_SLEEP_VALUES</span><br><span> select SOUTHBRIDGE_INTEL_COMMON</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOUTHBRIDGE_INTEL_COMMON_FINALIZE</span><br><span> select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ</span><br><span> select SOUTHBRIDGE_INTEL_COMMON_SMBUS</span><br><span> select SOUTHBRIDGE_INTEL_COMMON_SPI</span><br><span>@@ -67,42 +68,3 @@</span><br><span> default 0x80</span><br><span> </span><br><span> endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216 || SOUTHBRIDGE_INTEL_IBEXPEAK</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-choice</span><br><span style="color: hsl(0, 100%, 40%);">- prompt "Flash locking during chipset lockdown"</span><br><span style="color: hsl(0, 100%, 40%);">- default LOCK_SPI_FLASH_NONE</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config LOCK_SPI_FLASH_NONE</span><br><span style="color: hsl(0, 100%, 40%);">- bool "Don't lock flash sections"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config LOCK_SPI_FLASH_RO</span><br><span style="color: hsl(0, 100%, 40%);">- bool "Write-protect all flash sections"</span><br><span style="color: hsl(0, 100%, 40%);">- help</span><br><span style="color: hsl(0, 100%, 40%);">- Select this if you want to write-protect the whole firmware flash</span><br><span style="color: hsl(0, 100%, 40%);">- chip. The locking will take place during the chipset lockdown, which</span><br><span style="color: hsl(0, 100%, 40%);">- is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set)</span><br><span style="color: hsl(0, 100%, 40%);">- or has to be triggered later (e.g. by the payload or the OS).</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- NOTE: If you trigger the chipset lockdown unconditionally,</span><br><span style="color: hsl(0, 100%, 40%);">- you won't be able to write to the flash chip using the</span><br><span style="color: hsl(0, 100%, 40%);">- internal programmer any more.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config LOCK_SPI_FLASH_NO_ACCESS</span><br><span style="color: hsl(0, 100%, 40%);">- bool "Write-protect all flash sections and read-protect non-BIOS sections"</span><br><span style="color: hsl(0, 100%, 40%);">- help</span><br><span style="color: hsl(0, 100%, 40%);">- Select this if you want to protect the firmware flash against all</span><br><span style="color: hsl(0, 100%, 40%);">- further accesses (with the exception of the memory mapped BIOS re-</span><br><span style="color: hsl(0, 100%, 40%);">- gion which is always readable). The locking will take place during</span><br><span style="color: hsl(0, 100%, 40%);">- the chipset lockdown, which is either triggered by coreboot (when</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_CHIPSET_LOCKDOWN is set) or has to be triggered later (e.g.</span><br><span style="color: hsl(0, 100%, 40%);">- by the payload or the OS).</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- NOTE: If you trigger the chipset lockdown unconditionally,</span><br><span style="color: hsl(0, 100%, 40%);">- you won't be able to write to the flash chip using the</span><br><span style="color: hsl(0, 100%, 40%);">- internal programmer any more.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-endchoice</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-endif</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc</span><br><span>index c00b2c4..24d7e2d 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/Makefile.inc</span><br><span>+++ b/src/southbridge/intel/bd82x6x/Makefile.inc</span><br><span>@@ -35,7 +35,7 @@</span><br><span> </span><br><span> ramstage-$(CONFIG_ELOG) += elog.c</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c pch.c</span><br><span style="color: hsl(120, 100%, 40%);">+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c pch.c</span><br><span> </span><br><span> romstage-y += early_smbus.c me_status.c</span><br><span> romstage-y += early_spi.c early_pch_common.c</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h</span><br><span>index bb0d5c4..280ac7d 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/pch.h</span><br><span>+++ b/src/southbridge/intel/bd82x6x/pch.h</span><br><span>@@ -56,10 +56,6 @@</span><br><span> #ifndef __ACPI__</span><br><span> #define DEBUG_PERIODIC_SMIS 0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if defined(__SMM__) && !defined(__ASSEMBLER__)</span><br><span style="color: hsl(0, 100%, 40%);">-void intel_pch_finalize_smm(void);</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #if !defined(__ASSEMBLER__)</span><br><span> #if !defined(__PRE_RAM__)</span><br><span> #if !defined(__SIMPLE_DEVICE__)</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c</span><br><span>index 03d2687..6291867 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/smihandler.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/smihandler.c</span><br><span>@@ -32,6 +32,7 @@</span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <cpu/intel/model_206ax/model_206ax.h></span><br><span> #include <southbridge/intel/common/pmutil.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/finalize.h></span><br><span> </span><br><span> static global_nvs_t *gnvs;</span><br><span> global_nvs_t *smm_get_gnvs(void)</span><br><span>diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig</span><br><span>index 957faa5..ba53f68 100644</span><br><span>--- a/src/southbridge/intel/common/Kconfig</span><br><span>+++ b/src/southbridge/intel/common/Kconfig</span><br><span>@@ -33,6 +33,9 @@</span><br><span> config SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT</span><br><span> bool</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config SOUTHBRIDGE_INTEL_COMMON_FINALIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config INTEL_DESCRIPTOR_MODE_CAPABLE</span><br><span> def_bool n</span><br><span> help</span><br><span>@@ -55,3 +58,42 @@</span><br><span> locked down on each normal boot path (done by either coreboot or payload)</span><br><span> and S3 resume (always done by coreboot). Select this to let coreboot</span><br><span> to do this on normal boot path.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+if SOUTHBRIDGE_INTEL_COMMON_FINALIZE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+choice</span><br><span style="color: hsl(120, 100%, 40%);">+ prompt "Flash locking during chipset lockdown"</span><br><span style="color: hsl(120, 100%, 40%);">+ default LOCK_SPI_FLASH_NONE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config LOCK_SPI_FLASH_NONE</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "Don't lock flash sections"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config LOCK_SPI_FLASH_RO</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "Write-protect all flash sections"</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ Select this if you want to write-protect the whole firmware flash</span><br><span style="color: hsl(120, 100%, 40%);">+ chip. The locking will take place during the chipset lockdown, which</span><br><span style="color: hsl(120, 100%, 40%);">+ is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set)</span><br><span style="color: hsl(120, 100%, 40%);">+ or has to be triggered later (e.g. by the payload or the OS).</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ NOTE: If you trigger the chipset lockdown unconditionally,</span><br><span style="color: hsl(120, 100%, 40%);">+ you won't be able to write to the flash chip using the</span><br><span style="color: hsl(120, 100%, 40%);">+ internal programmer any more.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config LOCK_SPI_FLASH_NO_ACCESS</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "Write-protect all flash sections and read-protect non-BIOS sections"</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ Select this if you want to protect the firmware flash against all</span><br><span style="color: hsl(120, 100%, 40%);">+ further accesses (with the exception of the memory mapped BIOS re-</span><br><span style="color: hsl(120, 100%, 40%);">+ gion which is always readable). The locking will take place during</span><br><span style="color: hsl(120, 100%, 40%);">+ the chipset lockdown, which is either triggered by coreboot (when</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_CHIPSET_LOCKDOWN is set) or has to be triggered later (e.g.</span><br><span style="color: hsl(120, 100%, 40%);">+ by the payload or the OS).</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ NOTE: If you trigger the chipset lockdown unconditionally,</span><br><span style="color: hsl(120, 100%, 40%);">+ you won't be able to write to the flash chip using the</span><br><span style="color: hsl(120, 100%, 40%);">+ internal programmer any more.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endchoice</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endif</span><br><span>diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc</span><br><span>index b87354c..1a509b1 100644</span><br><span>--- a/src/southbridge/intel/common/Makefile.inc</span><br><span>+++ b/src/southbridge/intel/common/Makefile.inc</span><br><span>@@ -54,6 +54,8 @@</span><br><span> </span><br><span> ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT) += madt.c</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE) += finalize.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> romstage-y += rtc.c</span><br><span> ramstage-y += rtc.c</span><br><span> postcar-y += rtc.c</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/common/finalize.c</span><br><span>similarity index 67%</span><br><span>rename from src/southbridge/intel/bd82x6x/finalize.c</span><br><span>rename to src/southbridge/intel/common/finalize.c</span><br><span>index a08535e..f1c33b9 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/finalize.c</span><br><span>+++ b/src/southbridge/intel/common/finalize.c</span><br><span>@@ -15,24 +15,25 @@</span><br><span> */</span><br><span> </span><br><span> #include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ops.h></span><br><span> #include <console/post_codes.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/smm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_ops.h></span><br><span> #include <southbridge/intel/common/pmbase.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/pmutil.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> #include <spi-generic.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "chip.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include "pch.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include "finalize.h"</span><br><span> </span><br><span> void intel_pch_finalize_smm(void)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ const pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> if (IS_ENABLED(CONFIG_LOCK_SPI_FLASH_RO) ||</span><br><span> IS_ENABLED(CONFIG_LOCK_SPI_FLASH_NO_ACCESS)) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Copy flash regions from FREG0-4 to PR0-4</span><br><span style="color: hsl(0, 100%, 40%);">- and enable write protection bit31 */</span><br><span> int i;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 lockmask = (1 << 31);</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 lockmask = 1UL << 31;</span><br><span> if (IS_ENABLED(CONFIG_LOCK_SPI_FLASH_NO_ACCESS))</span><br><span style="color: hsl(0, 100%, 40%);">- lockmask |= (1 << 15);</span><br><span style="color: hsl(120, 100%, 40%);">+ lockmask |= 1 << 15;</span><br><span> for (i = 0; i < 20; i += 4)</span><br><span> RCBA32(0x3874 + i) = RCBA32(0x3854 + i) | lockmask;</span><br><span> }</span><br><span>@@ -40,13 +41,12 @@</span><br><span> /* Lock SPIBAR */</span><br><span> RCBA32_OR(0x3804, (1 << 15));</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)</span><br><span style="color: hsl(0, 100%, 40%);">- /* Re-init SPI driver to handle locked BAR */</span><br><span style="color: hsl(0, 100%, 40%);">- spi_init();</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_SPI_FLASH_SMM))</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Re-init SPI driver to handle locked BAR */</span><br><span style="color: hsl(120, 100%, 40%);">+ spi_init();</span><br><span> </span><br><span> /* TCLOCKDN: TC Lockdown */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32_OR(0x0050, (1 << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32_OR(0x0050, (1UL << 31));</span><br><span> </span><br><span> /* BIOS Interface Lockdown */</span><br><span> RCBA32_OR(0x3410, (1 << 0));</span><br><span>@@ -54,23 +54,23 @@</span><br><span> /* Function Disable SUS Well Lockdown */</span><br><span> RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7));</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Global SMI Lock */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_or_config16(PCH_LPC_DEV, GEN_PMCON_1, 1 << 4);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_or_config16(lpc_dev, D31F0_GEN_PMCON_1, SMI_LOCK);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* GEN_PMCON Lock */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_or_config8(PCH_LPC_DEV, GEN_PMCON_LOCK, (1 << 1) | (1 << 2));</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_or_config8(lpc_dev, D31F0_GEN_PMCON_LOCK,</span><br><span style="color: hsl(120, 100%, 40%);">+ ACPI_BASE_LOCK | SLP_STR_POL_LOCK);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* ETR3: CF9GR Lockdown */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_update_config32(PCH_LPC_DEV, ETR3, ~ETR3_CF9GR, ETR3_CF9LOCK);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_update_config32(lpc_dev, D31F0_ETR3, ~ETR3_CF9GR, ETR3_CF9LOCK);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT))</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PMSYNC */</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32_OR(0x33c4, (1UL << 31));</span><br><span> </span><br><span> /* R/WO registers */</span><br><span> RCBA32(0x21a4) = RCBA32(0x21a4);</span><br><span> pci_write_config32(PCI_DEV(0, 27, 0), 0x74,</span><br><span> pci_read_config32(PCI_DEV(0, 27, 0), 0x74));</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* TCO_Lock */</span><br><span> write_pmbase16(TCO1_CNT, read_pmbase16(TCO1_CNT) | TCO_LOCK);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Indicate finalize step with post code */</span><br><span style="color: hsl(0, 100%, 40%);">- outb(POST_OS_BOOT, 0x80);</span><br><span style="color: hsl(120, 100%, 40%);">+ outb(POST_OS_BOOT, CONFIG_POST_IO_PORT);</span><br><span> }</span><br><span>diff --git a/src/southbridge/intel/common/finalize.h b/src/southbridge/intel/common/finalize.h</span><br><span>new file mode 100644</span><br><span>index 0000000..4a8cbc0</span><br><span>--- /dev/null</span><br><span>+++ b/src/southbridge/intel/common/finalize.h</span><br><span>@@ -0,0 +1,22 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef SOUTHBRIDGE_INTEL_COMMON_FINALIZE_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define SOUTHBRIDGE_INTEL_COMMON_FINALIZE_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void intel_pch_finalize_smm(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* SOUTHBRIDGE_INTEL_COMMON_FINALIZE_H */</span><br><span>diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h</span><br><span>index 2e761cc..47813f7 100644</span><br><span>--- a/src/southbridge/intel/common/pmutil.h</span><br><span>+++ b/src/southbridge/intel/common/pmutil.h</span><br><span>@@ -20,10 +20,20 @@</span><br><span> #include <cpu/x86/smm.h></span><br><span> </span><br><span> #define D31F0_PMBASE 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+#define D31F0_GEN_PMCON_1 0xa0</span><br><span style="color: hsl(120, 100%, 40%);">+#define SMI_LOCK (1 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define D31F0_GEN_PMCON_2 0xa2</span><br><span> #define D31F0_GEN_PMCON_3 0xa4</span><br><span> #define RTC_BATTERY_DEAD (1 << 2)</span><br><span> #define RTC_POWER_FAILED (1 << 1)</span><br><span> #define SLEEP_AFTER_POWER_FAIL (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define D31F0_GEN_PMCON_LOCK 0xa6</span><br><span style="color: hsl(120, 100%, 40%);">+#define ACPI_BASE_LOCK (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SLP_STR_POL_LOCK (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define D31F0_ETR3 0xac</span><br><span style="color: hsl(120, 100%, 40%);">+#define ETR3_CWORWRE (1 << 18)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ETR3_CF9GR (1 << 20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ETR3_CF9LOCK (1 << 31)</span><br><span> #define D31F0_GPIO_ROUT 0xb8</span><br><span> #define GPI_DISABLE 0x00</span><br><span> #define GPI_IS_SMI 0x01</span><br><span>diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig</span><br><span>index fe6526d..7e2254e 100644</span><br><span>--- a/src/southbridge/intel/ibexpeak/Kconfig</span><br><span>+++ b/src/southbridge/intel/ibexpeak/Kconfig</span><br><span>@@ -28,6 +28,7 @@</span><br><span> select PCIEXP_ASPM</span><br><span> select PCIEXP_COMMON_CLOCK</span><br><span> select SOUTHBRIDGE_INTEL_COMMON</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOUTHBRIDGE_INTEL_COMMON_FINALIZE</span><br><span> select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ</span><br><span> select SOUTHBRIDGE_INTEL_COMMON_SMBUS</span><br><span> select SOUTHBRIDGE_INTEL_COMMON_SPI</span><br><span>diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc</span><br><span>index 906652d..5c89030 100644</span><br><span>--- a/src/southbridge/intel/ibexpeak/Makefile.inc</span><br><span>+++ b/src/southbridge/intel/ibexpeak/Makefile.inc</span><br><span>@@ -37,7 +37,7 @@</span><br><span> ramstage-y += madt.c</span><br><span> </span><br><span> ramstage-y += smi.c</span><br><span style="color: hsl(0, 100%, 40%);">-smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x6x/finalize.c ../bd82x6x/pch.c</span><br><span style="color: hsl(120, 100%, 40%);">+smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x6x/pch.c</span><br><span> </span><br><span> romstage-y += ../bd82x6x/early_usb.c early_smbus.c ../bd82x6x/early_me.c ../bd82x6x/me_status.c ../common/gpio.c early_thermal.c</span><br><span> romstage-y += ../bd82x6x/early_rcba.c</span><br><span>diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h</span><br><span>index 55478b9..35bf0ca 100644</span><br><span>--- a/src/southbridge/intel/ibexpeak/pch.h</span><br><span>+++ b/src/southbridge/intel/ibexpeak/pch.h</span><br><span>@@ -51,10 +51,6 @@</span><br><span> #ifndef __ACPI__</span><br><span> #define DEBUG_PERIODIC_SMIS 0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if defined(__SMM__) && !defined(__ASSEMBLER__)</span><br><span style="color: hsl(0, 100%, 40%);">-void intel_pch_finalize_smm(void);</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #if !defined(__ASSEMBLER__)</span><br><span> #if !defined(__PRE_RAM__)</span><br><span> #if !defined(__SIMPLE_DEVICE__)</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig</span><br><span>index 5b06c4b..b331ba1 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/Kconfig</span><br><span>+++ b/src/southbridge/intel/lynxpoint/Kconfig</span><br><span>@@ -25,6 +25,7 @@</span><br><span> select SOUTHBRIDGE_INTEL_COMMON_SMBUS</span><br><span> select SOUTHBRIDGE_INTEL_COMMON_SPI</span><br><span> select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOUTHBRIDGE_INTEL_COMMON_FINALIZE</span><br><span> select IOAPIC</span><br><span> select HAVE_USBDEBUG_OPTIONS</span><br><span> select USE_WATCHDOG_ON_BOOT</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc</span><br><span>index db34546..c2a49fd 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/Makefile.inc</span><br><span>+++ b/src/southbridge/intel/lynxpoint/Makefile.inc</span><br><span>@@ -42,7 +42,7 @@</span><br><span> ramstage-$(CONFIG_ELOG) += elog.c</span><br><span> </span><br><span> ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c pmutil.c</span><br><span style="color: hsl(0, 100%, 40%);">-smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c finalize.c pch.c</span><br><span style="color: hsl(120, 100%, 40%);">+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c pch.c</span><br><span> smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c usb_ehci.c usb_xhci.c</span><br><span> </span><br><span> romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/finalize.c b/src/southbridge/intel/lynxpoint/finalize.c</span><br><span>deleted file mode 100644</span><br><span>index 590a245..0000000</span><br><span>--- a/src/southbridge/intel/lynxpoint/finalize.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,68 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(0, 100%, 40%);">- * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(0, 100%, 40%);">- * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(0, 100%, 40%);">- * the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ops.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/post_codes.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <spi-generic.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "me.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include "pch.h"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void intel_pch_finalize_smm(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Lock down Management Engine */</span><br><span style="color: hsl(0, 100%, 40%);">- intel_me_finalize_smm();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set SPI opcode menu */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA16(0x3894) = SPI_OPPREFIX;</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA16(0x3896) = SPI_OPTYPE;</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(0x3898) = SPI_OPMENU_LOWER;</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(0x389c) = SPI_OPMENU_UPPER;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Lock SPIBAR */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32_OR(0x3804, (1 << 15));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)</span><br><span style="color: hsl(0, 100%, 40%);">- /* Re-init SPI driver to handle locked BAR */</span><br><span style="color: hsl(0, 100%, 40%);">- spi_init();</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* TCLOCKDN: TC Lockdown */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32_OR(0x0050, (1UL << 31));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* BIOS Interface Lockdown */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32_OR(0x3410, (1 << 0));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Function Disable SUS Well Lockdown */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Global SMI Lock */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GEN_PMCON Lock */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* PMSYNC */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32_OR(PMSYNC_CONFIG, (1UL << 31));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* R/WO registers */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(0x21a4) = RCBA32(0x21a4);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 27, 0), 0x74,</span><br><span style="color: hsl(0, 100%, 40%);">- pci_read_config32(PCI_DEV(0, 27, 0), 0x74));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Indicate finalize step with post code */</span><br><span style="color: hsl(0, 100%, 40%);">- outb(POST_OS_BOOT, 0x80);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c</span><br><span>index 437db81..d914636 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/lpc.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/lpc.c</span><br><span>@@ -969,6 +969,11 @@</span><br><span> </span><br><span> static void lpc_final(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA16(0x3894) = SPI_OPPREFIX;</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA16(0x3896) = SPI_OPTYPE;</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32(0x3898) = SPI_OPMENU_LOWER;</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32(0x389c) = SPI_OPMENU_UPPER;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> if (acpi_is_wakeup_s3() || IS_ENABLED(CONFIG_INTEL_CHIPSET_LOCKDOWN))</span><br><span> outb(APM_CNT_FINALIZE, APM_CNT);</span><br><span> }</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h</span><br><span>index a02be81..a28d703 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/pch.h</span><br><span>+++ b/src/southbridge/intel/lynxpoint/pch.h</span><br><span>@@ -92,7 +92,6 @@</span><br><span> #ifndef __ACPI__</span><br><span> </span><br><span> #if defined(__SMM__) && !defined(__ASSEMBLER__)</span><br><span style="color: hsl(0, 100%, 40%);">-void intel_pch_finalize_smm(void);</span><br><span> void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);</span><br><span> void usb_ehci_disable(pci_devfn_t dev);</span><br><span> void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c</span><br><span>index 12e5ea2..a3965d0 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/smihandler.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/smihandler.c</span><br><span>@@ -25,8 +25,10 @@</span><br><span> #include <elog.h></span><br><span> #include <halt.h></span><br><span> #include <pc80/mc146818rtc.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/finalize.h></span><br><span> #include <northbridge/intel/haswell/haswell.h></span><br><span> #include <cpu/intel/haswell/haswell.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "me.h"</span><br><span> #include "pch.h"</span><br><span> </span><br><span> #include "nvs.h"</span><br><span>@@ -284,6 +286,7 @@</span><br><span> return;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ intel_me_finalize_smm();</span><br><span> intel_pch_finalize_smm();</span><br><span> intel_northbridge_haswell_finalize_smm();</span><br><span> intel_cpu_haswell_finalize_smm();</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/29977">change 29977</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/29977"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I781082b1ed507b00815d1e85aec3e56ae5a4bef2 </div>
<div style="display:none"> Gerrit-Change-Number: 29977 </div>
<div style="display:none"> Gerrit-PatchSet: 4 </div>
<div style="display:none"> Gerrit-Owner: Tristan Corrick <tristan@corrick.kiwi> </div>
<div style="display:none"> Gerrit-Reviewer: Alexander Couzens <lynxis@fe80.eu> </div>
<div style="display:none"> Gerrit-Reviewer: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-Reviewer: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Nico Huber <nico.h@gmx.de> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> </div>
<div style="display:none"> Gerrit-Reviewer: Tristan Corrick <tristan@corrick.kiwi> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-MessageType: merged </div>