<p>Patrick Georgi <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/c/coreboot/+/29976">View Change</a></p><div style="white-space:pre-wrap">Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved

</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/lynxpoint: Ensure the finalise handler is called<br><br>The finalise handler is not called during S3 resume when using the<br>`BS_PAYLOAD_BOOT` approach. So, adopt the `lpc_final` approach used by<br>bd82x6x and others.<br><br>Tested on an ASRock H81M-HDS. The finalise handler is now called on<br>the normal boot path, and during S3 resume.<br><br>Change-Id: I9766a8dcbcb38420e937c810d252fef071851e92<br>Signed-off-by: Tristan Corrick <tristan@corrick.kiwi><br>Reviewed-on: https://review.coreboot.org/c/29976<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Nico Huber <nico.h@gmx.de><br>---<br>M src/southbridge/intel/lynxpoint/lpc.c<br>M src/southbridge/intel/lynxpoint/smi.c<br>2 files changed, 6 insertions(+), 14 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c</span><br><span>index ca850c0..437db81 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/lpc.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/lpc.c</span><br><span>@@ -967,6 +967,11 @@</span><br><span>      return current;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static void lpc_final(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+        if (acpi_is_wakeup_s3() || IS_ENABLED(CONFIG_INTEL_CHIPSET_LOCKDOWN))</span><br><span style="color: hsl(120, 100%, 40%);">+         outb(APM_CNT_FINALIZE, APM_CNT);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span> </span><br><span> static struct pci_operations pci_ops = {</span><br><span>  .set_subsystem = set_subsystem,</span><br><span>@@ -981,6 +986,7 @@</span><br><span>        .acpi_name              = lpc_acpi_name,</span><br><span>     .write_acpi_tables      = southbridge_write_acpi_tables,</span><br><span>     .init                   = lpc_init,</span><br><span style="color: hsl(120, 100%, 40%);">+   .final                  = lpc_final,</span><br><span>         .enable                 = pch_lpc_enable,</span><br><span>    .scan_bus               = scan_lpc_bus,</span><br><span>      .ops_pci                = &pci_ops,</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c</span><br><span>index 5dab05c..cf70d21 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/smi.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/smi.c</span><br><span>@@ -118,17 +118,3 @@</span><br><span>                "d" (APM_CNT)</span><br><span>    );</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * Finalize system before payload boot if INTEL_CHIPSET_LOCKDOWN=y</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-#if IS_ENABLED(CONFIG_INTEL_CHIPSET_LOCKDOWN)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void finalize_boot(void *unused)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">-     outb(APM_CNT_FINALIZE, APM_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/29976">change 29976</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/29976"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I9766a8dcbcb38420e937c810d252fef071851e92 </div>
<div style="display:none"> Gerrit-Change-Number: 29976 </div>
<div style="display:none"> Gerrit-PatchSet: 3 </div>
<div style="display:none"> Gerrit-Owner: Tristan Corrick <tristan@corrick.kiwi> </div>
<div style="display:none"> Gerrit-Reviewer: Nico Huber <nico.h@gmx.de> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> </div>
<div style="display:none"> Gerrit-Reviewer: Tristan Corrick <tristan@corrick.kiwi> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-MessageType: merged </div>