<p>HAOUAS Elyes has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/29990">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/{bd82x6x,i82801gx,ibexpeak,lynxpoint}: Use BIOS_CNTL macro<br><br>Use BIOS_CNTL defined macro instead of magic number.<br><br>Change-Id: I0d2b555ada9c2893af4f85422128f5a8b04e2fc6<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/southbridge/intel/bd82x6x/lpc.c<br>M src/southbridge/intel/i82801gx/lpc.c<br>M src/southbridge/intel/ibexpeak/lpc.c<br>M src/southbridge/intel/lynxpoint/lpc.c<br>4 files changed, 12 insertions(+), 12 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/29990/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c</span><br><span>index 7ae538e..16969e9 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/lpc.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/lpc.c</span><br><span>@@ -436,9 +436,9 @@</span><br><span>         u8 reg8;</span><br><span> </span><br><span>         printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... ");</span><br><span style="color: hsl(0, 100%, 40%);">-        reg8 = pci_read_config8(dev, 0xdc);     /* BIOS_CNTL */</span><br><span style="color: hsl(120, 100%, 40%);">+       reg8 = pci_read_config8(dev, BIOS_CNTL);</span><br><span>     reg8 &= ~(1 << 5);</span><br><span style="color: hsl(0, 100%, 40%);">-    pci_write_config8(dev, 0xdc, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+   pci_write_config8(dev, BIOS_CNTL, reg8);</span><br><span> }</span><br><span> </span><br><span> static void pch_fixups(struct device *dev)</span><br><span>diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c</span><br><span>index 7dcec50..c44697d 100644</span><br><span>--- a/src/southbridge/intel/i82801gx/lpc.c</span><br><span>+++ b/src/southbridge/intel/i82801gx/lpc.c</span><br><span>@@ -358,15 +358,15 @@</span><br><span> #if TEST_SMM_FLASH_LOCKDOWN</span><br><span>  /* Now try this: */</span><br><span>  printk(BIOS_DEBUG, "Locking BIOS to RO... ");</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = pci_read_config8(dev, 0xdc);     /* BIOS_CNTL */</span><br><span style="color: hsl(120, 100%, 40%);">+       reg8 = pci_read_config8(dev, BIOS_CNTL);</span><br><span>     printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",</span><br><span>                     (reg8&1)?"rw":"ro");</span><br><span>         reg8 &= ~(1 << 0);                    /* clear BIOSWE */</span><br><span style="color: hsl(0, 100%, 40%);">-      pci_write_config8(dev, 0xdc, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+   pci_write_config8(dev, BIOS_CNTL, reg8);</span><br><span>     reg8 |= (1 << 1);                 /* set BLE */</span><br><span style="color: hsl(0, 100%, 40%);">-   pci_write_config8(dev, 0xdc, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+   pci_write_config8(dev, BIOS_CNTL, reg8);</span><br><span>     printk(BIOS_DEBUG, "ok.\n");</span><br><span style="color: hsl(0, 100%, 40%);">-  reg8 = pci_read_config8(dev, 0xdc);     /* BIOS_CNTL */</span><br><span style="color: hsl(120, 100%, 40%);">+       reg8 = pci_read_config8(dev, BIOS_CNTL);</span><br><span>     printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",</span><br><span>                     (reg8&1)?"rw":"ro");</span><br><span> </span><br><span>@@ -374,9 +374,9 @@</span><br><span>       *(volatile u8 *)0xfff00000 = 0x00;</span><br><span>   printk(BIOS_DEBUG, "Testing:\n");</span><br><span>  reg8 |= (1 << 0);                 /* set BIOSWE */</span><br><span style="color: hsl(0, 100%, 40%);">-        pci_write_config8(dev, 0xdc, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+   pci_write_config8(dev, BIOS_CNTL, reg8);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-    reg8 = pci_read_config8(dev, 0xdc);     /* BIOS_CNTL */</span><br><span style="color: hsl(120, 100%, 40%);">+       reg8 = pci_read_config8(dev, BIOS_CNTL);</span><br><span>     printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",</span><br><span>                     (reg8&1)?"rw":"ro");</span><br><span>         printk(BIOS_DEBUG, "Done.\n");</span><br><span>diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c</span><br><span>index e5cbc59..d0361f6 100644</span><br><span>--- a/src/southbridge/intel/ibexpeak/lpc.c</span><br><span>+++ b/src/southbridge/intel/ibexpeak/lpc.c</span><br><span>@@ -449,9 +449,9 @@</span><br><span>  u8 reg8;</span><br><span> </span><br><span>         printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... ");</span><br><span style="color: hsl(0, 100%, 40%);">-        reg8 = pci_read_config8(dev, 0xdc);     /* BIOS_CNTL */</span><br><span style="color: hsl(120, 100%, 40%);">+       reg8 = pci_read_config8(dev, BIOS_CNTL);</span><br><span>     reg8 &= ~(1 << 5);</span><br><span style="color: hsl(0, 100%, 40%);">-    pci_write_config8(dev, 0xdc, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+   pci_write_config8(dev, BIOS_CNTL, reg8);</span><br><span> }</span><br><span> </span><br><span> static void pch_fixups(struct device *dev)</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c</span><br><span>index ca850c0..75d64b7 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/lpc.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/lpc.c</span><br><span>@@ -510,9 +510,9 @@</span><br><span>       u8 reg8;</span><br><span> </span><br><span>         printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... ");</span><br><span style="color: hsl(0, 100%, 40%);">-        reg8 = pci_read_config8(dev, 0xdc);     /* BIOS_CNTL */</span><br><span style="color: hsl(120, 100%, 40%);">+       reg8 = pci_read_config8(dev, BIOS_CNTL);</span><br><span>     reg8 &= ~(1 << 5);</span><br><span style="color: hsl(0, 100%, 40%);">-    pci_write_config8(dev, 0xdc, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+   pci_write_config8(dev, BIOS_CNTL, reg8);</span><br><span> }</span><br><span> </span><br><span> static void pch_fixups(struct device *dev)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/29990">change 29990</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/29990"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I0d2b555ada9c2893af4f85422128f5a8b04e2fc6 </div>
<div style="display:none"> Gerrit-Change-Number: 29990 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: HAOUAS Elyes <ehaouas@noos.fr> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>