<p>Philipp Deppenwiese <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/c/coreboot/+/29840">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Werner Zeh: Looks good to me, approved
Julius Werner: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">security/vboot: Fix remaining measured boot issues<br><br>Makes vboot measured boot mode available for all boards.<br><br>* Increase Tegra210 and Rockchip3228 SRAM for<br> romstage/verstage.<br>* Add missing files for Intel apollolake and<br> AMD stoneyridge as TPM driver target.<br><br>Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82<br>Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com><br>Reviewed-on: https://review.coreboot.org/c/29840<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Werner Zeh <werner.zeh@siemens.com><br>Reviewed-by: Julius Werner <jwerner@chromium.org><br>---<br>M src/soc/amd/stoneyridge/Makefile.inc<br>M src/soc/intel/apollolake/Makefile.inc<br>M src/soc/nvidia/tegra210/include/soc/memlayout.ld<br>M src/soc/rockchip/rk3288/include/soc/memlayout.ld<br>4 files changed, 14 insertions(+), 12 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc</span><br><span>index c54b652..a53984e 100644</span><br><span>--- a/src/soc/amd/stoneyridge/Makefile.inc</span><br><span>+++ b/src/soc/amd/stoneyridge/Makefile.inc</span><br><span>@@ -87,6 +87,7 @@</span><br><span> postcar-y += ramtop.c</span><br><span> postcar-y += sb_util.c</span><br><span> postcar-y += nb_util.c</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c</span><br><span> </span><br><span> ramstage-y += BiosCallOuts.c</span><br><span> ramstage-y += i2c.c</span><br><span>diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc</span><br><span>index 6168f86..19ebe7c 100644</span><br><span>--- a/src/soc/intel/apollolake/Makefile.inc</span><br><span>+++ b/src/soc/intel/apollolake/Makefile.inc</span><br><span>@@ -75,6 +75,7 @@</span><br><span> postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += heci.c</span><br><span> postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += reset.c</span><br><span> postcar-$(CONFIG_UART_DEBUG) += uart.c</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += gspi.c</span><br><span> </span><br><span> verstage-y += car.c</span><br><span> verstage-y += i2c.c</span><br><span>diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout.ld b/src/soc/nvidia/tegra210/include/soc/memlayout.ld</span><br><span>index c1c581b..d807c06 100644</span><br><span>--- a/src/soc/nvidia/tegra210/include/soc/memlayout.ld</span><br><span>+++ b/src/soc/nvidia/tegra210/include/soc/memlayout.ld</span><br><span>@@ -28,18 +28,18 @@</span><br><span> SECTIONS</span><br><span> {</span><br><span> SRAM_START(0x40000000)</span><br><span style="color: hsl(0, 100%, 40%);">- PRERAM_CBMEM_CONSOLE(0x40000000, 8K)</span><br><span style="color: hsl(0, 100%, 40%);">- PRERAM_CBFS_CACHE(0x40002000, 36K)</span><br><span style="color: hsl(0, 100%, 40%);">- VBOOT2_WORK(0x4000B000, 12K)</span><br><span style="color: hsl(120, 100%, 40%);">+ PRERAM_CBMEM_CONSOLE(0x40000000, 4K)</span><br><span style="color: hsl(120, 100%, 40%);">+ PRERAM_CBFS_CACHE(0x40001000, 36K)</span><br><span style="color: hsl(120, 100%, 40%);">+ VBOOT2_WORK(0x4000A000, 12K)</span><br><span> #if ENV_ARM64</span><br><span style="color: hsl(0, 100%, 40%);">- STACK(0x4000E000, 3K)</span><br><span style="color: hsl(120, 100%, 40%);">+ STACK(0x4000D000, 3K)</span><br><span> #else /* AVP gets a separate stack to avoid any chance of handoff races. */</span><br><span style="color: hsl(0, 100%, 40%);">- STACK(0x4000EC00, 3K)</span><br><span style="color: hsl(120, 100%, 40%);">+ STACK(0x4000DC00, 3K)</span><br><span> #endif</span><br><span style="color: hsl(0, 100%, 40%);">- TIMESTAMP(0x4000F800, 2K)</span><br><span style="color: hsl(0, 100%, 40%);">- BOOTBLOCK(0x40010000, 28K)</span><br><span style="color: hsl(0, 100%, 40%);">- VERSTAGE(0x40017000, 64K)</span><br><span style="color: hsl(0, 100%, 40%);">- ROMSTAGE(0x40027000, 100K)</span><br><span style="color: hsl(120, 100%, 40%);">+ TIMESTAMP(0x4000E800, 2K)</span><br><span style="color: hsl(120, 100%, 40%);">+ BOOTBLOCK(0x4000F000, 28K)</span><br><span style="color: hsl(120, 100%, 40%);">+ VERSTAGE(0x40016000, 64K)</span><br><span style="color: hsl(120, 100%, 40%);">+ ROMSTAGE(0x40026000, 104K)</span><br><span> SRAM_END(0x40040000)</span><br><span> </span><br><span> DRAM_START(0x80000000)</span><br><span>diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld</span><br><span>index fc3758b..6320fad 100644</span><br><span>--- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld</span><br><span>+++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld</span><br><span>@@ -31,9 +31,9 @@</span><br><span> SRAM_START(0xFF700000)</span><br><span> TTB(0xFF700000, 16K)</span><br><span> BOOTBLOCK(0xFF704004, 20K - 4)</span><br><span style="color: hsl(0, 100%, 40%);">- PRERAM_CBMEM_CONSOLE(0xFF709000, 3K)</span><br><span style="color: hsl(0, 100%, 40%);">- VBOOT2_WORK(0xFF709C00, 12K)</span><br><span style="color: hsl(0, 100%, 40%);">- OVERLAP_VERSTAGE_ROMSTAGE(0xFF70CC00, 41K)</span><br><span style="color: hsl(120, 100%, 40%);">+ PRERAM_CBMEM_CONSOLE(0xFF709000, 2K)</span><br><span style="color: hsl(120, 100%, 40%);">+ VBOOT2_WORK(0xFF709800, 12K)</span><br><span style="color: hsl(120, 100%, 40%);">+ OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C800, 42K)</span><br><span> PRERAM_CBFS_CACHE(0xFF717000, 1K)</span><br><span> TIMESTAMP(0xFF717400, 0x180)</span><br><span> STACK(0xFF717580, 3K - 0x180)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/29840">change 29840</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82 </div>
<div style="display:none"> Gerrit-Change-Number: 29840 </div>
<div style="display:none"> Gerrit-PatchSet: 18 </div>
<div style="display:none"> Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Julius Werner <jwerner@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> </div>
<div style="display:none"> Gerrit-Reviewer: Paul Menzel <paulepanter@users.sourceforge.net> </div>
<div style="display:none"> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Werner Zeh <werner.zeh@siemens.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-CC: Aaron Durbin <adurbin@chromium.org> </div>
<div style="display:none"> Gerrit-MessageType: merged </div>