<p>nsekar@codeaurora.org has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/29962">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">qcs405: clock: Adding the clock support for qcs405<br><br>Add basic clock support and enable UART, SPI clocks.<br><br>Change-Id: I991bdde5f69e1c0f6ec5d6961275a1c077bc5bae<br>Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org><br>Signed-off-by: Pranav Agrawal <pranava@codeaurora.org><br>Signed-off-by: Sricharan R <sricharan@codeaurora.org><br>---<br>M src/soc/qualcomm/qcs405/Makefile.inc<br>M src/soc/qualcomm/qcs405/bootblock.c<br>A src/soc/qualcomm/qcs405/clock.c<br>A src/soc/qualcomm/qcs405/include/soc/clock.h<br>4 files changed, 367 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/29962/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc</span><br><span>index 6fc87c7..58a62fa 100644</span><br><span>--- a/src/soc/qualcomm/qcs405/Makefile.inc</span><br><span>+++ b/src/soc/qualcomm/qcs405/Makefile.inc</span><br><span>@@ -7,6 +7,7 @@</span><br><span> bootblock-y += mmu.c</span><br><span> bootblock-y += timer.c</span><br><span> bootblock-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += clock.c</span><br><span> bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c</span><br><span> bootblock-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c</span><br><span> </span><br><span>@@ -22,6 +23,7 @@</span><br><span> romstage-y += cbmem.c</span><br><span> romstage-y += timer.c</span><br><span> romstage-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += clock.c</span><br><span> romstage-y += mmu.c</span><br><span> romstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c</span><br><span> romstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c</span><br><span>@@ -32,6 +34,7 @@</span><br><span> ramstage-y += cbmem.c</span><br><span> ramstage-y += timer.c</span><br><span> ramstage-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += clock.c</span><br><span> ramstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c</span><br><span> ramstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c</span><br><span> </span><br><span>diff --git a/src/soc/qualcomm/qcs405/bootblock.c b/src/soc/qualcomm/qcs405/bootblock.c</span><br><span>index 5e63f13..15d1c18 100644</span><br><span>--- a/src/soc/qualcomm/qcs405/bootblock.c</span><br><span>+++ b/src/soc/qualcomm/qcs405/bootblock.c</span><br><span>@@ -15,6 +15,12 @@</span><br><span> </span><br><span> #include <bootblock_common.h></span><br><span> #include <soc/mmu.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/clock.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_soc_early_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ clock_init();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span> </span><br><span> void bootblock_soc_init(void)</span><br><span> {</span><br><span>diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c</span><br><span>new file mode 100644</span><br><span>index 0000000..6307259</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/qualcomm/qcs405/clock.c</span><br><span>@@ -0,0 +1,208 @@</span><br><span style="color: hsl(120, 100%, 40%);">+ /* This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Qualcomm Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License version 2 and</span><br><span style="color: hsl(120, 100%, 40%);">+ * only version 2 as published by the Free Software Foundation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <types.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <delay.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <timer.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <timestamp.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <commonlib/helpers.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/clock.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DIV(div) (div ? (2*div - 1) : 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define HALF_DIVIDER(div2x) (div2x ? (div2x - 1) : 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct clock_config uart_cfg[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ .hz = 1843200,</span><br><span style="color: hsl(120, 100%, 40%);">+ .hw_ctl = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .src = SRC_GPLL0_MAIN_800MHZ,</span><br><span style="color: hsl(120, 100%, 40%);">+ .div = DIV(0),</span><br><span style="color: hsl(120, 100%, 40%);">+ .m = 36,</span><br><span style="color: hsl(120, 100%, 40%);">+ .n = 15625,</span><br><span style="color: hsl(120, 100%, 40%);">+ .d_2 = 15625,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ .hz = 3686400,</span><br><span style="color: hsl(120, 100%, 40%);">+ .hw_ctl = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .src = SRC_GPLL0_MAIN_800MHZ,</span><br><span style="color: hsl(120, 100%, 40%);">+ .div = DIV(0),</span><br><span style="color: hsl(120, 100%, 40%);">+ .m = 72,</span><br><span style="color: hsl(120, 100%, 40%);">+ .n = 15625,</span><br><span style="color: hsl(120, 100%, 40%);">+ .d_2 = 15625,</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct clock_config i2c_cfg[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ .hz = 19200000,</span><br><span style="color: hsl(120, 100%, 40%);">+ .hw_ctl = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .src = SRC_XO_19_2MHZ,</span><br><span style="color: hsl(120, 100%, 40%);">+ .div = DIV(0),</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ .hz = 50000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ .hw_ctl = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .src = SRC_GPLL0_MAIN_800MHZ,</span><br><span style="color: hsl(120, 100%, 40%);">+ .div = DIV(32),</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct clock_config spi_cfg[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ .hz = 19200000,</span><br><span style="color: hsl(120, 100%, 40%);">+ .hw_ctl = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .src = SRC_XO_19_2MHZ,</span><br><span style="color: hsl(120, 100%, 40%);">+ .div = DIV(0),</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ .hz = 30000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ .hw_ctl = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .src = SRC_XO_19_2MHZ,</span><br><span style="color: hsl(120, 100%, 40%);">+ .div = DIV(0),</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ .hz = 50000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ .hw_ctl = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .src = SRC_GPLL0_MAIN_800MHZ,</span><br><span style="color: hsl(120, 100%, 40%);">+ .div = DIV(32),</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct qcs405_clock *const blsp1_uart2_clk =</span><br><span style="color: hsl(120, 100%, 40%);">+ (void *)GCC_BLSP1_UART2_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct qcs405_clock *const blsp2_qup0_spi_clk =</span><br><span style="color: hsl(120, 100%, 40%);">+ (void *)GCC_BLSP2_QUP0_SPI_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static int clock_configure_mnd(struct qcs405_clock *clk, uint32_t m, uint32_t n,</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t d_2)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reg_val;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Configure Root Clock Generator(RCG) for Dual Edge Mode */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg_val = read32(&clk->cfg_rcgr);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg_val |= (2 << CLK_CTL_CFG_MODE_SHFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&clk->cfg_rcgr, reg_val);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set M/N/D config */</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&clk->m, m & CLK_CTL_RCG_MND_BMSK);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&clk->n, ~(n-m) & CLK_CTL_RCG_MND_BMSK);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&clk->d_2, ~(d_2) & CLK_CTL_RCG_MND_BMSK);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static int clock_configure(struct qcs405_clock *clk,</span><br><span style="color: hsl(120, 100%, 40%);">+ struct clock_config *clk_cfg,</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t hz, uint32_t num_perfs)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reg_val;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t idx;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (idx = 0; idx < num_perfs; idx++)</span><br><span style="color: hsl(120, 100%, 40%);">+ if (hz <= clk_cfg[idx].hz)</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ reg_val = (clk_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (clk_cfg[idx].div << CLK_CTL_CFG_SRC_DIV_SHFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set clock config */</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&clk->cfg_rcgr, reg_val);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (clk_cfg[idx].m != 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ clock_configure_mnd(clk, clk_cfg[idx].m, clk_cfg[idx].n,</span><br><span style="color: hsl(120, 100%, 40%);">+ clk_cfg[idx].d_2);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Commit config to RCG*/</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&clk->cmd_rcgr, BIT(CLK_CTL_CMD_UPDATE_SHFT));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static bool clock_is_off(void *cbcr_addr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return (read32(cbcr_addr) & CLK_CTL_CBC_CLK_OFF_BMSK);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static int clock_enable_vote(void *cbcr_addr, void *vote_addr,</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t vote_bit)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set clock vote bit */</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(vote_addr, BIT(vote_bit));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Ensure clock is enabled */</span><br><span style="color: hsl(120, 100%, 40%);">+ while (clock_is_off(cbcr_addr))</span><br><span style="color: hsl(120, 100%, 40%);">+ ;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static int clock_enable(void *cbcr_addr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set clock enable bit */</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Ensure clock is enabled */</span><br><span style="color: hsl(120, 100%, 40%);">+ while (clock_is_off(cbcr_addr))</span><br><span style="color: hsl(120, 100%, 40%);">+ ;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static int clock_disable(void *cbcr_addr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set clock enable bit */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int clock_reset_bcr(void *bcr_addr, bool reset)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct qcs405_bcr *bcr = bcr_addr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (reset)</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&bcr->bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&bcr->bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void clock_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clock_configure(blsp1_uart2_clk, uart_cfg, 1843200,</span><br><span style="color: hsl(120, 100%, 40%);">+ ARRAY_SIZE(uart_cfg));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clock_disable(REG(GCC_BLSP1_UART0_APPS_CBCR));</span><br><span style="color: hsl(120, 100%, 40%);">+ clock_enable(REG(GCC_BLSP1_UART0_APPS_CBCR));</span><br><span style="color: hsl(120, 100%, 40%);">+ clock_enable(REG(GCC_BLSP1_UART2_APPS_CBCR));</span><br><span style="color: hsl(120, 100%, 40%);">+ clock_enable_vote(REG(GCC_BLSP1_AHB_CBCR),</span><br><span style="color: hsl(120, 100%, 40%);">+ REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE),</span><br><span style="color: hsl(120, 100%, 40%);">+ BLSP1_AHB_CLK_ENA);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clock_configure(blsp2_qup0_spi_clk, spi_cfg, 50000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ ARRAY_SIZE(spi_cfg));</span><br><span style="color: hsl(120, 100%, 40%);">+ clock_enable(REG(GCC_BLSP2_QUP0_SPI_APPS_CBCR));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>diff --git a/src/soc/qualcomm/qcs405/include/soc/clock.h b/src/soc/qualcomm/qcs405/include/soc/clock.h</span><br><span>new file mode 100644</span><br><span>index 0000000..aa8bbe5</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/qualcomm/qcs405/include/soc/clock.h</span><br><span>@@ -0,0 +1,150 @@</span><br><span style="color: hsl(120, 100%, 40%);">+ /* This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Qualcomm Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License version 2 and</span><br><span style="color: hsl(120, 100%, 40%);">+ * only version 2 as published by the Free Software Foundation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __SOC_QUALCOMM_QCS405_CLOCK_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#define __SOC_QUALCOMM_QCS405_CLOCK_H__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_APCS_CLOCK_BRANCH_ENA_VOTE 0x01845004</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_BLSP1_UART0_BASE 0x180600C</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_BLSP1_UART1_BASE 0x1802044</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_BLSP1_UART2_BASE 0x1803034</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_BLSP1_UART3_BASE 0x1804014</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_BLSP2_UART0_BASE 0x180C044</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_BLSP1_QUP0_SPI_BASE 0x1806034</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_BLSP1_QUP1_SPI_BASE 0x1802024</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_BLSP1_QUP2_SPI_BASE 0x1803014</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_BLSP1_QUP3_SPI_BASE 0x1804024</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_BLSP1_QUP4_SPI_BASE 0x1805024</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_BLSP2_QUP0_SPI_BASE 0x180C024</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_BLSP1_QUP0_I2C_BASE 0x180602C</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_BLSP1_QUP1_I2C_BASE 0x180200C</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_BLSP1_QUP2_I2C_BASE 0x1803000</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_BLSP1_QUP3_I2C_BASE 0x1804000</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_BLSP1_QUP4_I2C_BASE 0x1805000</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_BLSP2_QUP0_I2C_BASE 0x180C00C</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_BLSP1_UART0_APPS_CBCR 0x1806004</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_BLSP1_UART1_APPS_CBCR 0x180203C</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_BLSP1_UART2_APPS_CBCR 0x180302C</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_BLSP1_UART3_APPS_CBCR 0x180400C</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_BLSP2_UART0_APPS_CBCR 0x180C03C</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_BLSP2_QUP0_SPI_APPS_CBCR 0x180C004</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_BLSP1_AHB_CBCR 0x1801008</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_BLSP2_AHB_CBCR 0x180B008</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLSP1_AHB_CLK_ENA 10</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLSP2_AHB_CLK_ENA 20</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SRC_XO_19_2MHZ 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define SRC_GPLL0_MAIN_800MHZ 1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1 0x0015200C</span><br><span style="color: hsl(120, 100%, 40%);">+#define SRC_XO_19_2MHZ 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define REG(addr) ((void *)addr)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * USB BCR registers</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_USB_HS_PHY_CFG_AHB_BCR 0x1841038</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_USB_HS_BCR 0x1841000</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_USB_30_BCR 0x1839000</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_USB2A_PHY_BCR 0x1841028</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_USB2_HS_PHY_ONLY_BCR 0x1841034</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_QUSB2_PHY_BCR 0x184103C</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct qcs405_clock {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t cmd_rcgr;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t cfg_rcgr;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t m;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t n;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t d_2;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct qcs405_bcr {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t bcr;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct mdss_clock_config {</span><br><span style="color: hsl(120, 100%, 40%);">+ const char *clk_name;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct qcs405_clock *rcgr;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t *cbcr;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum clk_ctl_gpll_user_ctl {</span><br><span style="color: hsl(120, 100%, 40%);">+ CLK_CTL_GPLL_PLLOUT_EVEN_BMSK = 0x2,</span><br><span style="color: hsl(120, 100%, 40%);">+ CLK_CTL_GPLL_PLLOUT_EVEN_SHFT = 1</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum clk_ctl_cfg_rcgr {</span><br><span style="color: hsl(120, 100%, 40%);">+ CLK_CTL_CFG_HW_CTL_BMSK = 0x100000,</span><br><span style="color: hsl(120, 100%, 40%);">+ CLK_CTL_CFG_HW_CTL_SHFT = 20,</span><br><span style="color: hsl(120, 100%, 40%);">+ CLK_CTL_CFG_MODE_BMSK = 0x3000,</span><br><span style="color: hsl(120, 100%, 40%);">+ CLK_CTL_CFG_MODE_SHFT = 12,</span><br><span style="color: hsl(120, 100%, 40%);">+ CLK_CTL_CFG_SRC_SEL_BMSK = 0x700,</span><br><span style="color: hsl(120, 100%, 40%);">+ CLK_CTL_CFG_SRC_SEL_SHFT = 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ CLK_CTL_CFG_SRC_DIV_BMSK = 0x1F,</span><br><span style="color: hsl(120, 100%, 40%);">+ CLK_CTL_CFG_SRC_DIV_SHFT = 0</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum clk_ctl_cmd_rcgr {</span><br><span style="color: hsl(120, 100%, 40%);">+ CLK_CTL_CMD_ROOT_OFF_BMSK = 0x80000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ CLK_CTL_CMD_ROOT_OFF_SHFT = 31,</span><br><span style="color: hsl(120, 100%, 40%);">+ CLK_CTL_CMD_ROOT_EN_BMSK = 0x2,</span><br><span style="color: hsl(120, 100%, 40%);">+ CLK_CTL_CMD_ROOT_EN_SHFT = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ CLK_CTL_CMD_UPDATE_BMSK = 0x1,</span><br><span style="color: hsl(120, 100%, 40%);">+ CLK_CTL_CMD_UPDATE_SHFT = 0</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum clk_ctl_cbcr {</span><br><span style="color: hsl(120, 100%, 40%);">+ CLK_CTL_CBC_CLK_OFF_BMSK = 0x80000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ CLK_CTL_CBC_CLK_OFF_SHFT = 31,</span><br><span style="color: hsl(120, 100%, 40%);">+ CLK_CTL_CBC_CLK_EN_BMSK = 0x1,</span><br><span style="color: hsl(120, 100%, 40%);">+ CLK_CTL_CBC_CLK_EN_SHFT = 0</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum clk_ctl_rcg_mnd {</span><br><span style="color: hsl(120, 100%, 40%);">+ CLK_CTL_RCG_MND_BMSK = 0xFFFF,</span><br><span style="color: hsl(120, 100%, 40%);">+ CLK_CTL_RCG_MND_SHFT = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum clk_ctl_bcr {</span><br><span style="color: hsl(120, 100%, 40%);">+ CLK_CTL_BCR_BLK_ARES_BMSK = 0x1,</span><br><span style="color: hsl(120, 100%, 40%);">+ CLK_CTL_BCR_BLK_ARES_SHFT = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct clock_config {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t hz;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t hw_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t src;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t div;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t m;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t n;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t d_2;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void clock_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void clock_reset_aop(void);</span><br><span style="color: hsl(120, 100%, 40%);">+int clock_configure_qspi(uint32_t hz);</span><br><span style="color: hsl(120, 100%, 40%);">+int clock_reset_bcr(void *bcr_addr, bool reset);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif // __SOC_QUALCOMM_QCS405_CLOCK_H__</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/29962">change 29962</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I991bdde5f69e1c0f6ec5d6961275a1c077bc5bae </div>
<div style="display:none"> Gerrit-Change-Number: 29962 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: nsekar@codeaurora.org </div>
<div style="display:none"> Gerrit-Reviewer: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: nsekar@codeaurora.org </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>