<p>nsekar@codeaurora.org has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/29955">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">qcs405: Add GPIO API<br><br>Introduces new and required GPIO APIs, using common pinmux<br>definitions for GPIO configuration.<br><br>TEST=build & run<br><br>Change-Id: I85ce9007c545b44371c4704a0456774d0eff12a8<br>Signed-off-by: Sricharan R <sricharan@codeaurora.org><br>Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org><br>---<br>M src/soc/qualcomm/qcs405/Makefile.inc<br>A src/soc/qualcomm/qcs405/gpio.c<br>A src/soc/qualcomm/qcs405/include/soc/addressmap.h<br>M src/soc/qualcomm/qcs405/include/soc/gpio.h<br>4 files changed, 436 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/29955/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc</span><br><span>index b47a61e..131f204 100644</span><br><span>--- a/src/soc/qualcomm/qcs405/Makefile.inc</span><br><span>+++ b/src/soc/qualcomm/qcs405/Makefile.inc</span><br><span>@@ -6,21 +6,25 @@</span><br><span> bootblock-y += spi.c</span><br><span> bootblock-y += mmu.c</span><br><span> bootblock-y += timer.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += gpio.c</span><br><span> </span><br><span> ################################################################################</span><br><span> verstage-y += spi.c</span><br><span> verstage-y += timer.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += gpio.c</span><br><span> </span><br><span> ################################################################################</span><br><span> romstage-y += spi.c</span><br><span> romstage-y += cbmem.c</span><br><span> romstage-y += timer.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += gpio.c</span><br><span> </span><br><span> ################################################################################</span><br><span> ramstage-y += soc.c</span><br><span> ramstage-y += spi.c</span><br><span> ramstage-y += cbmem.c</span><br><span> ramstage-y += timer.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += gpio.c</span><br><span> </span><br><span> ################################################################################</span><br><span> </span><br><span>diff --git a/src/soc/qualcomm/qcs405/gpio.c b/src/soc/qualcomm/qcs405/gpio.c</span><br><span>new file mode 100644</span><br><span>index 0000000..edbb3b9</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/qualcomm/qcs405/gpio.c</span><br><span>@@ -0,0 +1,76 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Qualcomm Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <types.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <delay.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <timer.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <timestamp.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull,</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t drive_str, uint32_t enable)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reg_val;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ reg_val = ((enable & GPIO_CFG_OE_BMSK) << GPIO_CFG_OE_SHFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((drive_str & GPIO_CFG_DRV_BMSK) << GPIO_CFG_DRV_SHFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((func & GPIO_CFG_FUNC_BMSK) << GPIO_CFG_FUNC_SHFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((pull & GPIO_CFG_PULL_BMSK) << GPIO_CFG_PULL_SHFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(®s->cfg, reg_val);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void gpio_set(gpio_t gpio, int value)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr;</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(®s->in_out, (!!value) << GPIO_IO_OUT_SHFT);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int gpio_get(gpio_t gpio)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return ((read32(®s->in_out) >> GPIO_IO_IN_SHFT) &</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_IO_IN_BMSK);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void gpio_input_pulldown(gpio_t gpio)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_configure(gpio, GPIO_FUNC_DISABLE,</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_PULL_DOWN, GPIO_2MA, GPIO_DISABLE);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void gpio_input_pullup(gpio_t gpio)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_configure(gpio, GPIO_FUNC_DISABLE,</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_PULL_UP, GPIO_2MA, GPIO_DISABLE);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void gpio_input(gpio_t gpio)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_configure(gpio, GPIO_FUNC_DISABLE,</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NO_PULL, GPIO_2MA, GPIO_DISABLE);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void gpio_output(gpio_t gpio, int value)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set(gpio, value);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_configure(gpio, GPIO_FUNC_DISABLE,</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NO_PULL, GPIO_2MA, GPIO_ENABLE);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/qualcomm/qcs405/include/soc/addressmap.h b/src/soc/qualcomm/qcs405/include/soc/addressmap.h</span><br><span>new file mode 100644</span><br><span>index 0000000..435b680</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/qualcomm/qcs405/include/soc/addressmap.h</span><br><span>@@ -0,0 +1,26 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (c) 2018 Qualcomm Technologies</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License version 2 and</span><br><span style="color: hsl(120, 100%, 40%);">+ * only version 2 as published by the Free Software Foundation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __SOC_QUALCOMM_QCS405_ADDRESS_MAP_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#define __SOC_QUALCOMM_QCS405_ADDRESS_MAP_H__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define QSPI_BASE 0x88DF000</span><br><span style="color: hsl(120, 100%, 40%);">+#define TLMM_EAST_TILE_BASE 0x7B00000</span><br><span style="color: hsl(120, 100%, 40%);">+#define TLMM_NORTH_TILE_BASE 0x1300000</span><br><span style="color: hsl(120, 100%, 40%);">+#define TLMM_SOUTH_TILE_BASE 0x1000000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* __SOC_QUALCOMM_QCS405_ADDRESS_MAP_H__ */</span><br><span>diff --git a/src/soc/qualcomm/qcs405/include/soc/gpio.h b/src/soc/qualcomm/qcs405/include/soc/gpio.h</span><br><span>index e1ad453..f436595 100644</span><br><span>--- a/src/soc/qualcomm/qcs405/include/soc/gpio.h</span><br><span>+++ b/src/soc/qualcomm/qcs405/include/soc/gpio.h</span><br><span>@@ -17,7 +17,336 @@</span><br><span> #define _SOC_QUALCOMM_QCS405_GPIO_H_</span><br><span> </span><br><span> #include <types.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/addressmap.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-typedef u32 gpio_t;</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 addr;</span><br><span style="color: hsl(120, 100%, 40%);">+} gpio_t;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define TLMM_TILE_SIZE 0x00400000</span><br><span style="color: hsl(120, 100%, 40%);">+#define TLMM_GPIO_OFF_DELTA 0x00001000</span><br><span style="color: hsl(120, 100%, 40%);">+#define TLMM_GPIO_TILE_NUM 3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define TLMM_GPIO_IN_OUT_OFF 0x4</span><br><span style="color: hsl(120, 100%, 40%);">+#define TLMM_GPIO_ID_STATUS_OFF 0x10</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_FUNC_ENABLE 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_FUNC_DISABLE 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPIO TLMM: Direction */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INPUT 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_OUTPUT 1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPIO TLMM: Pullup/Pulldown */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_NO_PULL 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_PULL_DOWN 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_KEEPER 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_PULL_UP 3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPIO TLMM: Drive Strength */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_2MA 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_4MA 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_6MA 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_8MA 3</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_10MA 4</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_12MA 5</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_14MA 6</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_16MA 7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPIO TLMM: Status */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_DISABLE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_ENABLE 1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPIO TLMM: Mask */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_CFG_PULL_BMSK 0x3</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_CFG_FUNC_BMSK 0xF</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_CFG_DRV_BMSK 0x7</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_CFG_OE_BMSK 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPIO TLMM: Shift */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_CFG_PULL_SHFT 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_CFG_FUNC_SHFT 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_CFG_DRV_SHFT 6</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_CFG_OE_SHFT 9</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPIO IO: Mask */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_IO_IN_BMSK 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_IO_OUT_BMSK 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPIO IO: Shift */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_IO_IN_SHFT 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_IO_OUT_SHFT 1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPIO ID STATUS: Mask */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_ID_STATUS_BMSK 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPIO MAX Valid # */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_NUM_MAX 149</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_FUNC_GPIO 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO(num) ((gpio_t){.addr = GPIO##num##_ADDR})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIN(index, tlmm, func1, func2, func3, func4, func5, func6, func7) \</span><br><span style="color: hsl(120, 100%, 40%);">+GPIO##index##_ADDR = TLMM_##tlmm##_TILE_BASE + index * TLMM_GPIO_OFF_DELTA, \</span><br><span style="color: hsl(120, 100%, 40%);">+GPIO##index##_FUNC_##func1 = 1, \</span><br><span style="color: hsl(120, 100%, 40%);">+GPIO##index##_FUNC_##func2 = 2, \</span><br><span style="color: hsl(120, 100%, 40%);">+GPIO##index##_FUNC_##func3 = 3, \</span><br><span style="color: hsl(120, 100%, 40%);">+GPIO##index##_FUNC_##func4 = 4, \</span><br><span style="color: hsl(120, 100%, 40%);">+GPIO##index##_FUNC_##func5 = 5, \</span><br><span style="color: hsl(120, 100%, 40%);">+GPIO##index##_FUNC_##func6 = 6, \</span><br><span style="color: hsl(120, 100%, 40%);">+GPIO##index##_FUNC_##func7 = 7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(0, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(1, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(2, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(3, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(4, NORTH, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(5, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(6, NORTH, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(7, NORTH, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(8, EAST, QUP_L4_0_CS, GP_PDM_MIRB, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(9, EAST, QUP_L5_0_CS, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(10, EAST, MDP_VSYNC_P_MIRA, QUP_L6_0_CS, RES_3, RES_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(11, EAST, MDP_VSYNC_S_MIRA, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(12, SOUTH, MDP_VSYNC_E, RES_2, TSIF1_SYNC, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(13, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(14, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(15, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(16, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(17, NORTH, CCI_I2C_SDA0, QUP_L0, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(18, SOUTH, CCI_I2C_SCL0, QUP_L1, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(19, SOUTH, CCI_I2C_SDA1, QUP_L2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(20, SOUTH, CCI_I2C_SCL1, QUP_L3, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(21, SOUTH, CCI_TIMER0, GCC_GP2_CLK_MIRB, RES_3, RES_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(22, SOUTH, CCI_TIMER1, GCC_GP3_CLK_MIRB, RES_3, RES_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(23, SOUTH, CCI_TIMER2, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(24, SOUTH, CCI_TIMER3, CCI_ASYNC_IN1, RES_3, RES_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(25, SOUTH, CCI_TIMER4, CCI_ASYNC_IN2, RES_3, RES_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(26, SOUTH, CCI_ASYNC_IN0, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(27, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(28, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(29, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(30, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(31, NORTH, QUP_L0, QUP_L2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(32, NORTH, QUP_L1, QUP_L3, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(33, NORTH, QUP_L2, QUP_L0, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(34, NORTH, QUP_L3, QUP_L1, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(35, SOUTH, PCI_E0_RST_N, QUP_L4_1_CS, RES_3, RES_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(36, SOUTH, PCI_E0_CLKREQN, QUP_L5_1_CS, RES_3, RES_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(37, SOUTH, QUP_L6_1_CS, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(38, NORTH, USB_PHY_PS, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(39, EAST, LPASS_SLIMBUS_DATA2, RES_2, RES_3, RES_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(40, SOUTH, SD_WRITE_PROTECT, TSIF1_ERROR, RES_3, RES_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(41, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(42, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(43, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(44, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(45, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(46, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(47, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(48, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(49, NORTH, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(50, NORTH, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(51, NORTH, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(52, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(53, NORTH, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(54, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(55, NORTH, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(56, NORTH, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(57, NORTH, QUA_MI2S_MCLK, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(58, NORTH, QUA_MI2S_SCK, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(59, NORTH, QUA_MI2S_WS, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(60, NORTH, QUA_MI2S_DATA0, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(61, NORTH, QUA_MI2S_DATA1, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(62, NORTH, QUA_MI2S_DATA2, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(63, NORTH, QUA_MI2S_DATA3, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(64, NORTH, PRI_MI2S_MCLK, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(65, NORTH, PRI_MI2S_SCK, QUP_L0, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(66, NORTH, PRI_MI2S_WS, QUP_L1, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(67, NORTH, PRI_MI2S_DATA0, QUP_L2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(68, NORTH, PRI_MI2S_DATA1, QUP_L3, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(69, EAST, SPKR_I2S_MCLK, AUDIO_REF_CLK, RES_3, RES_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(70, EAST, LPASS_SLIMBUS_CLK, SPKR_I2S_SCK, RES_3, RES_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(71, EAST, LPASS_SLIMBUS_DATA0, SPKR_I2S_DATA_OUT, RES_3,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(72, EAST, LPASS_SLIMBUS_DATA1, SPKR_I2S_WS, RES_3, RES_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(73, EAST, BTFM_SLIMBUS_DATA, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(74, EAST, BTFM_SLIMBUS_CLK, TER_MI2S_MCLK, RES_3, RES_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(75, EAST, TER_MI2S_SCK, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(76, EAST, TER_MI2S_WS, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(77, EAST, TER_MI2S_DATA0, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(78, EAST, TER_MI2S_DATA1, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(79, NORTH, SEC_MI2S_MCLK, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(80, NORTH, SEC_MI2S_SCK, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(81, NORTH, SEC_MI2S_WS, QUP_L0, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(82, NORTH, SEC_MI2S_DATA0, QUP_L1, RES_3, RES_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(83, NORTH, SEC_MI2S_DATA1, QUP_L2, RES_3, RES_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(84, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(85, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(86, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(87, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(88, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(89, SOUTH, TSIF1_CLK, QUP_L0, QSPI_CS_N_1, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(90, SOUTH, TSIF1_EN, MDP_VSYNC0_OUT, QUP_L1, QSPI_CS_N_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ MDP_VSYNC1_OUT, MDP_VSYNC2_OUT, MDP_VSYNC3_OUT),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(91, SOUTH, TSIF1_DATA, SDC4_CMD, QUP_L2, QSPI_DATA,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(92, SOUTH, TSIF2_ERROR, SDC4_DATA, QUP_L3, QSPI_DATA,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(93, SOUTH, TSIF2_CLK, SDC4_CLK, QUP_L0, QSPI_DATA,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(94, SOUTH, TSIF2_EN, SDC4_DATA, QUP_L1, QSPI_DATA,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(95, SOUTH, TSIF2_DATA, SDC4_DATA, QUP_L2, QSPI_CLK,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(96, SOUTH, TSIF2_SYNC, SDC4_DATA, QUP_L3, RES_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(97, NORTH, RFFE6_CLK, GRFC37, MDP_VSYNC_P_MIRB,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(98, NORTH, RFFE6_DATA, MDP_VSYNC_S_MIRB, RES_3,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(99, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(100, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(101, NORTH, GRFC4, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(102, NORTH, PCI_E1_RST_N, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(103, NORTH, PCI_E1_CLKREQN, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(104, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(105, NORTH, UIM2_DATA, QUP_L0, QUP_L4_8_CS, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(106, NORTH, UIM2_CLK, QUP_L1, QUP_L5_8_CS, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(107, NORTH, UIM2_RESET, QUP_L2, QUP_L6_8_CS, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(108, NORTH, UIM2_PRESENT, QUP_L3, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(109, NORTH, UIM1_DATA, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(110, NORTH, UIM1_CLK, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(111, NORTH, UIM1_RESET, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(112, NORTH, UIM1_PRESENT, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(113, NORTH, UIM_BATT_ALARM, EDP_HOT_PLUG_DETECT, RES_3,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(114, NORTH, GRFC8, RES_2, RES_3, GPS_TX_AGGRESSOR_MIRE,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(115, NORTH, GRFC9, RES_2, RES_3, GPS_TX_AGGRESSOR_MIRF,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(116, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(117, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(118, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(119, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(120, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(121, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(122, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(123, EAST, QUP_L4_9_CS, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(124, EAST, QUP_L5_9_CS, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(125, EAST, QUP_L6_9_CS, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(126, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(127, NORTH, GRFC3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(128, NORTH, RES_1, RES_2, GPS_TX_AGGRESSOR_MIRB, RES_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(129, NORTH, RES_1, RES_2, GPS_TX_AGGRESSOR_MIRC, RES_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(130, NORTH, QLINK_REQUEST, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(131, NORTH, QLINK_ENABLE, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(132, NORTH, GRFC2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(133, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(134, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(135, NORTH, GRFC0, PA_INDICATOR_1_OR_2, RES_3, RES_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(136, NORTH, GRFC1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(137, NORTH, RFFE3_DATA, GRFC35, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(138, NORTH, RFFE3_CLK, GRFC32, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(139, NORTH, RFFE4_DATA, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(140, NORTH, RFFE4_CLK, GRFC36, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(141, NORTH, RFFE5_DATA, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(142, NORTH, RFFE5_CLK, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(143, NORTH, GRFC5, RES_2, RES_3, GPS_TX_AGGRESSOR_MIRD,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(144, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(145, NORTH, RES_1, GPS_TX_AGGRESSOR_MIRA, RES_3, RES_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_5, RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(146, NORTH, RFFE2_DATA, GRFC34, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(147, NORTH, RFFE2_CLK, GRFC33, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(148, NORTH, RFFE1_DATA, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PIN(149, NORTH, RFFE1_CLK, RES_2, RES_3, RES_4, RES_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_6, RES_7),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct tlmm_gpio {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t cfg;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t in_out;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull,</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t drive_str, uint32_t enable);</span><br><span> </span><br><span> #endif // _SOC_QUALCOMM_QCS405_GPIO_H_</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/29955">change 29955</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/29955"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I85ce9007c545b44371c4704a0456774d0eff12a8 </div>
<div style="display:none"> Gerrit-Change-Number: 29955 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: nsekar@codeaurora.org </div>
<div style="display:none"> Gerrit-Reviewer: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: nsekar@codeaurora.org </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>