<p>nsekar@codeaurora.org has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/29966">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Coreboot: Add support for USB host mode for mistral platform<br><br>Add required changes for USB host mode working on mistral platform for USB disk<br>enumeration.<br><br>Change-Id: I35ec549b49b9789389c80843f6103e7243d52aac<br>Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org><br>Signed-off-by: Vijayavardhan Vennapusa <vvreddy@partner-android.googlesource.com><br>Signed-off-by: Sricharan R <sricharan@codeaurora.org><br>---<br>M src/mainboard/google/mistral/mainboard.c<br>M src/mainboard/google/mistral/romstage.c<br>M src/soc/qualcomm/qcs405/Makefile.inc<br>M src/soc/qualcomm/qcs405/include/soc/addressmap.h<br>M src/soc/qualcomm/qcs405/include/soc/clock.h<br>M src/soc/qualcomm/qcs405/include/soc/iomap.h<br>A src/soc/qualcomm/qcs405/include/soc/usb.h<br>A src/soc/qualcomm/qcs405/usb.c<br>8 files changed, 370 insertions(+), 11 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/29966/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/mistral/mainboard.c b/src/mainboard/google/mistral/mainboard.c</span><br><span>index c249a32..7201874 100644</span><br><span>--- a/src/mainboard/google/mistral/mainboard.c</span><br><span>+++ b/src/mainboard/google/mistral/mainboard.c</span><br><span>@@ -16,10 +16,34 @@</span><br><span> #include <device/device.h></span><br><span> #include <bootblock_common.h></span><br><span> #include <timestamp.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/usb.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct usb_board_data usb0_board_data = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .parameter_override_x0 = 0x63,</span><br><span style="color: hsl(120, 100%, 40%);">+ .parameter_override_x1 = 0x03,</span><br><span style="color: hsl(120, 100%, 40%);">+ .parameter_override_x0 = 0x1d,</span><br><span style="color: hsl(120, 100%, 40%);">+ .parameter_override_x1 = 0x03,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct usb_board_data usb1_board_data = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .parameter_override_x0 = 0x63,</span><br><span style="color: hsl(120, 100%, 40%);">+ .parameter_override_x1 = 0x03,</span><br><span style="color: hsl(120, 100%, 40%);">+ .parameter_override_x0 = 0x1d,</span><br><span style="color: hsl(120, 100%, 40%);">+ .parameter_override_x1 = 0x03,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void setup_usb(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Setting Primarty usb controller */</span><br><span style="color: hsl(120, 100%, 40%);">+ setup_usb_host(HSUSB_SS_PORT_0, &usb0_board_data);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Setting secondary usb controller */</span><br><span style="color: hsl(120, 100%, 40%);">+ setup_usb_host(HSUSB_HS_PORT_1, &usb1_board_data);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span> </span><br><span> static void mainboard_init(device_t dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(120, 100%, 40%);">+ setup_usb();</span><br><span> }</span><br><span> </span><br><span> static void mainboard_enable(device_t dev)</span><br><span>diff --git a/src/mainboard/google/mistral/romstage.c b/src/mainboard/google/mistral/romstage.c</span><br><span>index 71968fc..31e5113 100644</span><br><span>--- a/src/mainboard/google/mistral/romstage.c</span><br><span>+++ b/src/mainboard/google/mistral/romstage.c</span><br><span>@@ -20,12 +20,19 @@</span><br><span> #include <console/console.h></span><br><span> #include <timestamp.h></span><br><span> #include <arch/stages.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/usb.h></span><br><span> </span><br><span> #ifdef CONFIG_QC_SOC_SIMULATE</span><br><span> extern void qcs405_mmu_dram_config_c(void);</span><br><span> #endif</span><br><span> void platform_romstage_main(void)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Do DWC3 core and phy reset. Kick these resets off early</span><br><span style="color: hsl(120, 100%, 40%);">+ * so they get atleast 1msec to settle.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ reset_usb(HSUSB_SS_PORT_0);</span><br><span style="color: hsl(120, 100%, 40%);">+ reset_usb(HSUSB_HS_PORT_1);</span><br><span> #ifdef CONFIG_QC_SOC_SIMULATE</span><br><span> qcs405_mmu_dram_config_c();</span><br><span> #endif</span><br><span>diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc</span><br><span>index 57d59f8..c174cae 100644</span><br><span>--- a/src/soc/qualcomm/qcs405/Makefile.inc</span><br><span>+++ b/src/soc/qualcomm/qcs405/Makefile.inc</span><br><span>@@ -27,6 +27,7 @@</span><br><span> romstage-y += mmu.c</span><br><span> romstage-$(CONFIG_DRIVERS_UART) += uart.c</span><br><span> romstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += usb.c</span><br><span> </span><br><span> ################################################################################</span><br><span> ramstage-y += soc.c</span><br><span>@@ -37,6 +38,7 @@</span><br><span> ramstage-y += clock.c</span><br><span> ramstage-$(CONFIG_DRIVERS_UART) += uart.c</span><br><span> ramstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += usb.c</span><br><span> </span><br><span> ################################################################################</span><br><span> </span><br><span>diff --git a/src/soc/qualcomm/qcs405/include/soc/addressmap.h b/src/soc/qualcomm/qcs405/include/soc/addressmap.h</span><br><span>index 435b680..696bc42 100644</span><br><span>--- a/src/soc/qualcomm/qcs405/include/soc/addressmap.h</span><br><span>+++ b/src/soc/qualcomm/qcs405/include/soc/addressmap.h</span><br><span>@@ -23,4 +23,12 @@</span><br><span> #define TLMM_NORTH_TILE_BASE 0x1300000</span><br><span> #define TLMM_SOUTH_TILE_BASE 0x1000000</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* USB BASE ADDRESS */</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB_HOST0_DWC3_BASE 0x758C100</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB3_USB30_QSCRATCH_BASE 0x7678800</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB2_FEMTO_PHY_PRI_BASE 0x007A000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB_HOST1_DWC3_BASE 0x78CC100</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB2_USB30_QSCRATCH_BASE 0x79B8800</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB2_FEMTO_PHY_SEC_BASE 0x007C000</span><br><span> #endif /* __SOC_QUALCOMM_QCS405_ADDRESS_MAP_H__ */</span><br><span>diff --git a/src/soc/qualcomm/qcs405/include/soc/clock.h b/src/soc/qualcomm/qcs405/include/soc/clock.h</span><br><span>index aa8bbe5..d02ecd7 100644</span><br><span>--- a/src/soc/qualcomm/qcs405/include/soc/clock.h</span><br><span>+++ b/src/soc/qualcomm/qcs405/include/soc/clock.h</span><br><span>@@ -65,10 +65,10 @@</span><br><span> /**</span><br><span> * USB BCR registers</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GCC_USB_HS_PHY_CFG_AHB_BCR 0x1841038</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_USB_HS_PHY_CFG_AHB_BCR 0x180000C</span><br><span> #define GCC_USB_HS_BCR 0x1841000</span><br><span> #define GCC_USB_30_BCR 0x1839000</span><br><span style="color: hsl(0, 100%, 40%);">-#define GCC_USB2A_PHY_BCR 0x1841028</span><br><span style="color: hsl(120, 100%, 40%);">+#define GCC_USB2A_PHY_BCR 0x180000C</span><br><span> #define GCC_USB2_HS_PHY_ONLY_BCR 0x1841034</span><br><span> #define GCC_QUSB2_PHY_BCR 0x184103C</span><br><span> </span><br><span>diff --git a/src/soc/qualcomm/qcs405/include/soc/iomap.h b/src/soc/qualcomm/qcs405/include/soc/iomap.h</span><br><span>index 2a7a148..571c62f 100644</span><br><span>--- a/src/soc/qualcomm/qcs405/include/soc/iomap.h</span><br><span>+++ b/src/soc/qualcomm/qcs405/include/soc/iomap.h</span><br><span>@@ -99,14 +99,6 @@</span><br><span> #define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 * (x))</span><br><span> #define GPIO_IN_OUT_ADDR(x) (GPIO_CONFIG_ADDR(x) + 4)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Yes, this is not a typo... host2 is actually mapped before host1. */</span><br><span style="color: hsl(0, 100%, 40%);">-#define USB_HOST2_XHCI_BASE 0x10000000</span><br><span style="color: hsl(0, 100%, 40%);">-#define USB_HOST2_DWC3_BASE 0x1000C100</span><br><span style="color: hsl(0, 100%, 40%);">-#define USB_HOST2_PHY_BASE 0x100F8800</span><br><span style="color: hsl(0, 100%, 40%);">-#define USB_HOST1_XHCI_BASE 0x11000000</span><br><span style="color: hsl(0, 100%, 40%);">-#define USB_HOST1_DWC3_BASE 0x1100C100</span><br><span style="color: hsl(0, 100%, 40%);">-#define USB_HOST1_PHY_BASE 0x110F8800</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #define UART1_DM_BASE ((void *)0x078af000)</span><br><span> #define UART2_DM_BASE ((void *)0x078B1000)</span><br><span> </span><br><span>diff --git a/src/soc/qualcomm/qcs405/include/soc/usb.h b/src/soc/qualcomm/qcs405/include/soc/usb.h</span><br><span>new file mode 100644</span><br><span>index 0000000..80674bb</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/qualcomm/qcs405/include/soc/usb.h</span><br><span>@@ -0,0 +1,76 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (c) 2018 Qualcomm Technologies</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License version 2 and</span><br><span style="color: hsl(120, 100%, 40%);">+ * only version 2 as published by the Free Software Foundation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#include <types.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _QCS405_USB_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _QCS405_USB_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* QSCRATCH_GENERAL_CFG register bit offset */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_UTMI_CLK_SEL BIT(0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE3_PHYSTATUS_SW BIT(3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIPE_UTMI_CLK_DIS BIT(8)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Global USB3 Control Registers */</span><br><span style="color: hsl(120, 100%, 40%);">+#define DWC3_GUSB3PIPECTL_DELAYP1TRANS BIT(18)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX BIT(27)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DWC3_GCTL_PRTCAP_OTG 3</span><br><span style="color: hsl(120, 100%, 40%);">+#define DWC3_GCTL_PRTCAP_HOST 1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Global USB2 PHY Configuration Register */</span><br><span style="color: hsl(120, 100%, 40%);">+#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define USBTRDTIM_UTMI_8_BIT 9</span><br><span style="color: hsl(120, 100%, 40%);">+#define UTMI_PHYIF_8_BIT 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DWC3_GCTL_DISSCRAMBLE (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DWC3_GCTL_U2EXIT_LFPS (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DWC3_GCTL_DSBLCLKGTNG (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB2 PHY register values */</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB2PHY_TCSR_CTRL 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB2PHY_REFCLK_CTRL 0x0d</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB2PHY_UTMI_CTRL5 0x12</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB2PHY_PARAMETER_OVERRIDE_X0 0x63</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB2PHY_PARAMETER_OVERRIDE_X1 0x03</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB2PHY_PARAMETER_OVERRIDE_X2 0x1d</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB2PHY_PARAMETER_OVERRIDE_X3 0x03</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB2PHY_HS_PHY_CTRL1 0x23</span><br><span style="color: hsl(120, 100%, 40%);">+#define QUSB2PHY_HS_PHY_CTRL_COMMON0 0x08</span><br><span style="color: hsl(120, 100%, 40%);">+#define QUSB2PHY_HS_PHY_CTRL_COMMON1 0xdc</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB2PHY_HS_PHY_CTRL2 0xe0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct usb_board_data {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Register values going to override from the boardfile */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 parameter_override_x0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 parameter_override_x1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 parameter_override_x2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 parameter_override_x3;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum usb_port {</span><br><span style="color: hsl(120, 100%, 40%);">+ HSUSB_SS_PORT_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ HSUSB_HS_PORT_1,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void setup_usb_host(enum usb_port port, struct usb_board_data *data);</span><br><span style="color: hsl(120, 100%, 40%);">+/* Call reset_ before setup_ */</span><br><span style="color: hsl(120, 100%, 40%);">+void reset_usb(enum usb_port port);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* _QCS405_USB_H_ */</span><br><span>diff --git a/src/soc/qualcomm/qcs405/usb.c b/src/soc/qualcomm/qcs405/usb.c</span><br><span>new file mode 100644</span><br><span>index 0000000..67574cf</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/qualcomm/qcs405/usb.c</span><br><span>@@ -0,0 +1,250 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (c) 2018 Qualcomm Technologies</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License version 2 and</span><br><span style="color: hsl(120, 100%, 40%);">+ * only version 2 as published by the Free Software Foundation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <lib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdlib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <delay.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/usb.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/clock.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/addressmap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <timer.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct usb_qscratch {</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 rsvd0[8];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 *qscratch_cfg_reg;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(usb_qscratch, qscratch_cfg_reg, 0x08);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct usb_usb2_phy_dig {</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 rsvd1[116];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 utmi_ctrl5;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ctrl_common0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ctrl_common1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 rsvd2[12];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 phy_ctrl1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 phy_ctrl2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 rsvd3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 override_x0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 override_x1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 override_x2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 override_x3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 rsvd4[24];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 tcsr_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 rsvd5[36];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 refclk_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(usb_usb2_phy_dig, utmi_ctrl5, 0x74);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(usb_usb2_phy_dig, phy_ctrl1, 0x8C);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(usb_usb2_phy_dig, override_x0, 0x98);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(usb_usb2_phy_dig, tcsr_ctrl, 0xC0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(usb_usb2_phy_dig, refclk_ctrl, 0xE8);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct usb_dwc3 {</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sbuscfg0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sbuscfg1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 txthrcfg;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 rxthrcfg;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pmsts;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sts;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 uctl1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 snpsid;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 gpio;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 uid;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 uctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 buserraddr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 prtbimap;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 reserved1[32];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dbgfifospace;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dbgltssm;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dbglnmcc;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dbgbmu;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dbglspmux;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dbglsp;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dbgepinfo0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dbgepinfo1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 prtbimap_hs;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 prtbimap_fs;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 reserved2[112];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 usb2phycfg;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 reserved3[60];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 usb2i2cctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 reserved4[60];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 usb2phyacc;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 reserved5[60];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 usb3pipectl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 reserved6[60];</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(usb_dwc3, usb3pipectl, 0x1c0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct usb_dwc3_cfg {</span><br><span style="color: hsl(120, 100%, 40%);">+ struct usb_dwc3 *usb_host_dwc3;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct usb_usb2_phy_dig *usb2_phy_dig;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct usb_qscratch *usb_qscratch_reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 *usb2_phy_bcr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 *usb2_phy_por_bcr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 *usb3_bcr;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct usb_board_data *board_data;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct usb_dwc3_cfg usb_host_base[2] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ [HSUSB_SS_PORT_0] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .usb_host_dwc3 = (void *)USB_HOST0_DWC3_BASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .usb2_phy_dig = (void *)USB2_FEMTO_PHY_PRI_BASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .usb2_phy_bcr = (void *)GCC_USB_HS_PHY_CFG_AHB_BCR,</span><br><span style="color: hsl(120, 100%, 40%);">+ .usb2_phy_por_bcr = (void *)GCC_USB2A_PHY_BCR,</span><br><span style="color: hsl(120, 100%, 40%);">+ .usb3_bcr = (void *)GCC_USB_30_BCR,</span><br><span style="color: hsl(120, 100%, 40%);">+ .usb_qscratch_reg = (void *)USB3_USB30_QSCRATCH_BASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ [HSUSB_HS_PORT_1] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .usb_host_dwc3 = (void *)USB_HOST1_DWC3_BASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .usb2_phy_dig = (void *)USB2_FEMTO_PHY_SEC_BASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .usb2_phy_bcr = (void *)GCC_QUSB2_PHY_BCR,</span><br><span style="color: hsl(120, 100%, 40%);">+ .usb2_phy_por_bcr = (void *)GCC_USB2_HS_PHY_ONLY_BCR,</span><br><span style="color: hsl(120, 100%, 40%);">+ .usb3_bcr = (void *)GCC_USB_HS_BCR,</span><br><span style="color: hsl(120, 100%, 40%);">+ .usb_qscratch_reg = (void *)USB2_USB30_QSCRATCH_BASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void reset_usb(enum usb_port port)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct usb_dwc3_cfg *dwc3 = &usb_host_base[port];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Put Core in Reset */</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "Starting DWC3 reset for USB%d\n", port);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Assert Core reset */</span><br><span style="color: hsl(120, 100%, 40%);">+ clock_reset_bcr(dwc3->usb3_bcr, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void usb2_phy_override_phy_params(struct usb_dwc3_cfg *dwc3)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ write8(&dwc3->usb2_phy_dig->override_x0, dwc3->board_data->parameter_override_x0);</span><br><span style="color: hsl(120, 100%, 40%);">+ write8(&dwc3->usb2_phy_dig->override_x1, dwc3->board_data->parameter_override_x1);</span><br><span style="color: hsl(120, 100%, 40%);">+ write8(&dwc3->usb2_phy_dig->override_x2, dwc3->board_data->parameter_override_x2);</span><br><span style="color: hsl(120, 100%, 40%);">+ write8(&dwc3->usb2_phy_dig->override_x3, dwc3->board_data->parameter_override_x3);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void hs_usb_phy_init(struct usb_dwc3_cfg *dwc3)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ write8(&dwc3->usb2_phy_dig->tcsr_ctrl, USB2PHY_TCSR_CTRL);</span><br><span style="color: hsl(120, 100%, 40%);">+ write8(&dwc3->usb2_phy_dig->refclk_ctrl, USB2PHY_REFCLK_CTRL);</span><br><span style="color: hsl(120, 100%, 40%);">+ write8(&dwc3->usb2_phy_dig->utmi_ctrl5, USB2PHY_UTMI_CTRL5);</span><br><span style="color: hsl(120, 100%, 40%);">+ write8(&dwc3->usb2_phy_dig->override_x0, USB2PHY_PARAMETER_OVERRIDE_X0);</span><br><span style="color: hsl(120, 100%, 40%);">+ write8(&dwc3->usb2_phy_dig->override_x1, USB2PHY_PARAMETER_OVERRIDE_X1);</span><br><span style="color: hsl(120, 100%, 40%);">+ write8(&dwc3->usb2_phy_dig->override_x2, USB2PHY_PARAMETER_OVERRIDE_X2);</span><br><span style="color: hsl(120, 100%, 40%);">+ write8(&dwc3->usb2_phy_dig->override_x3, USB2PHY_PARAMETER_OVERRIDE_X3);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dwc3->board_data)</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Overridw board specific PHY tuning values */</span><br><span style="color: hsl(120, 100%, 40%);">+ usb2_phy_override_phy_params(dwc3);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write8(&dwc3->usb2_phy_dig->phy_ctrl1, USB2PHY_HS_PHY_CTRL1);</span><br><span style="color: hsl(120, 100%, 40%);">+ write8(&dwc3->usb2_phy_dig->ctrl_common0, QUSB2PHY_HS_PHY_CTRL_COMMON0);</span><br><span style="color: hsl(120, 100%, 40%);">+ write8(&dwc3->usb2_phy_dig->ctrl_common1, QUSB2PHY_HS_PHY_CTRL_COMMON1);</span><br><span style="color: hsl(120, 100%, 40%);">+ write8(&dwc3->usb2_phy_dig->phy_ctrl2, USB2PHY_HS_PHY_CTRL2);</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(20);</span><br><span style="color: hsl(120, 100%, 40%);">+ write8(&dwc3->usb2_phy_dig->utmi_ctrl5, 0x10);</span><br><span style="color: hsl(120, 100%, 40%);">+ write8(&dwc3->usb2_phy_dig->phy_ctrl2, 0x60);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void setup_dwc3(struct usb_dwc3 *dwc3)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&dwc3->usb3pipectl,</span><br><span style="color: hsl(120, 100%, 40%);">+ DWC3_GUSB3PIPECTL_DELAYP1TRANS,</span><br><span style="color: hsl(120, 100%, 40%);">+ DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK |</span><br><span style="color: hsl(120, 100%, 40%);">+ DWC3_GCTL_DISSCRAMBLE),</span><br><span style="color: hsl(120, 100%, 40%);">+ DWC3_GCTL_U2EXIT_LFPS | DWC3_GCTL_DSBLCLKGTNG);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* configure controller in Host mode */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)),</span><br><span style="color: hsl(120, 100%, 40%);">+ DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_HOST));</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "Configure USB in Host mode\n");</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Initialization of DWC3 Core and PHY */</span><br><span style="color: hsl(120, 100%, 40%);">+void setup_usb_host(enum usb_port port, struct usb_board_data *board_data)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct usb_dwc3_cfg *dwc3 = &usb_host_base[port];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 val;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "Setting up USB HOST%d controller.\n", port);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dwc3->board_data = board_data;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Clear core reset. */</span><br><span style="color: hsl(120, 100%, 40%);">+ clock_reset_bcr(dwc3->usb3_bcr, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (port == HSUSB_SS_PORT_0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set PHY reset. */</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&dwc3->usb2_phy_bcr, BIT(1));</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(15);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Clear PHY reset. */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&dwc3->usb2_phy_bcr, BIT(1));</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ clock_reset_bcr(dwc3->usb2_phy_bcr, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(15);</span><br><span style="color: hsl(120, 100%, 40%);">+ clock_reset_bcr(dwc3->usb2_phy_bcr, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(100);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize PHYs */</span><br><span style="color: hsl(120, 100%, 40%);">+ hs_usb_phy_init(dwc3);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (port == HSUSB_SS_PORT_0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set PHY POR reset. */</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&dwc3->usb2_phy_por_bcr, BIT(0));</span><br><span style="color: hsl(120, 100%, 40%);">+ val = read8(&dwc3->usb2_phy_dig->ctrl_common0);</span><br><span style="color: hsl(120, 100%, 40%);">+ val &= ~(0x4);</span><br><span style="color: hsl(120, 100%, 40%);">+ write8(&dwc3->usb2_phy_dig->ctrl_common0, val);</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(20);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Clear PHY POR reset. */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&dwc3->usb2_phy_por_bcr, BIT(0));</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ clock_reset_bcr(dwc3->usb2_phy_por_bcr, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ val = read8(&dwc3->usb2_phy_dig->ctrl_common0);</span><br><span style="color: hsl(120, 100%, 40%);">+ val &= ~(0x4);</span><br><span style="color: hsl(120, 100%, 40%);">+ write8(&dwc3->usb2_phy_dig->ctrl_common0, val);</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(20);</span><br><span style="color: hsl(120, 100%, 40%);">+ clock_reset_bcr(dwc3->usb2_phy_por_bcr, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(100);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setup_dwc3(dwc3->usb_host_dwc3);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Below sequence is used when dwc3 operates without</span><br><span style="color: hsl(120, 100%, 40%);">+ * SSPHY and only HS/FS/LS modes are supported.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Configure dwc3 to use UTMI clock as PIPE clock not present */</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg,</span><br><span style="color: hsl(120, 100%, 40%);">+ PIPE_UTMI_CLK_DIS);</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(2);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg,</span><br><span style="color: hsl(120, 100%, 40%);">+ PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW);</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(3);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg,</span><br><span style="color: hsl(120, 100%, 40%);">+ PIPE_UTMI_CLK_DIS);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "DWC3 and PHY setup finished\n");</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/29966">change 29966</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/29966"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I35ec549b49b9789389c80843f6103e7243d52aac </div>
<div style="display:none"> Gerrit-Change-Number: 29966 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: nsekar@codeaurora.org </div>
<div style="display:none"> Gerrit-Reviewer: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: nsekar@codeaurora.org </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>