<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/29930">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/baytrail: Implement POSTCAR stage<br><br>Use common code to tear down CAR.<br><br>Change-Id: I62a70ae35fe92808f180f2b5f21c5899a96c2c16<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/soc/intel/baytrail/Kconfig<br>M src/soc/intel/baytrail/Makefile.inc<br>M src/soc/intel/baytrail/romstage/cache_as_ram.inc<br>M src/soc/intel/baytrail/romstage/romstage.c<br>4 files changed, 15 insertions(+), 90 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/29930/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig</span><br><span>index 66fcded..ece4d61 100644</span><br><span>--- a/src/soc/intel/baytrail/Kconfig</span><br><span>+++ b/src/soc/intel/baytrail/Kconfig</span><br><span>@@ -38,6 +38,8 @@</span><br><span> select HAVE_SPI_CONSOLE_SUPPORT</span><br><span> select INTEL_GMA_ACPI</span><br><span> select INTEL_GMA_SWSMISCI</span><br><span style="color: hsl(120, 100%, 40%);">+ select POSTCAR_STAGE</span><br><span style="color: hsl(120, 100%, 40%);">+ select POSTCAR_CONSOLE</span><br><span> </span><br><span> config VBOOT</span><br><span> select VBOOT_STARTS_IN_ROMSTAGE</span><br><span>diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc</span><br><span>index 324dcdd..3658f5a 100644</span><br><span>--- a/src/soc/intel/baytrail/Makefile.inc</span><br><span>+++ b/src/soc/intel/baytrail/Makefile.inc</span><br><span>@@ -10,6 +10,7 @@</span><br><span> </span><br><span> ramstage-y += memmap.c</span><br><span> romstage-y += memmap.c</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += memmap.c</span><br><span> ramstage-y += tsc_freq.c</span><br><span> romstage-y += tsc_freq.c</span><br><span> smm-y += tsc_freq.c</span><br><span>@@ -20,6 +21,7 @@</span><br><span> ramstage-y += iosf.c</span><br><span> romstage-y += iosf.c</span><br><span> smm-y += iosf.c</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += iosf.c</span><br><span> ramstage-y += northcluster.c</span><br><span> ramstage-y += ramstage.c</span><br><span> ramstage-y += gpio.c</span><br><span>@@ -51,6 +53,8 @@</span><br><span> # Remove as ramstage gets fleshed out</span><br><span> ramstage-y += placeholders.c</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += ../../../cpu/intel/car/non-evict/exit_car.S</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin</span><br><span> </span><br><span> CPPFLAGS_common += -Isrc/soc/intel/baytrail/include</span><br><span>diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc</span><br><span>index a2168ad..3bed040 100644</span><br><span>--- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc</span><br><span>+++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc</span><br><span>@@ -197,95 +197,11 @@</span><br><span> post_code(0x2a)</span><br><span> /* Call romstage.c main function. */</span><br><span> call romstage_main</span><br><span style="color: hsl(0, 100%, 40%);">- /* Save return value from romstage_main. It contains the stack to use</span><br><span style="color: hsl(0, 100%, 40%);">- * after cache-as-ram is torn down. It also contains the information</span><br><span style="color: hsl(0, 100%, 40%);">- * for setting up MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %ebx</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x2b)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- orl $CR0_CacheDisable, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x2c)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable MTRR. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_DEF_TYPE_MSR, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- andl $(~MTRR_DEF_TYPE_EN), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- invd</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x2d)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable the no eviction run state */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $NoEvictMod_MSR, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- andl $~2, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable the no eviction mode */</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- andl $~1, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x2e)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Setup stack as indicated by return value from romstage_main(). */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %ebx, %esp</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Get number of MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_PHYS_BASE(0), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">-1:</span><br><span style="color: hsl(0, 100%, 40%);">- testl %ebx, %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- jz 1f</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Low 32 bits of MTRR base. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %eax</span><br><span style="color: hsl(0, 100%, 40%);">- /* Upper 32 bits of MTRR base. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %edx</span><br><span style="color: hsl(0, 100%, 40%);">- /* Write MTRR base. */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">- inc %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- /* Low 32 bits of MTRR mask. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %eax</span><br><span style="color: hsl(0, 100%, 40%);">- /* Upper 32 bits of MTRR mask. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %edx</span><br><span style="color: hsl(0, 100%, 40%);">- /* Write MTRR mask. */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">- inc %ecx</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- dec %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- jmp 1b</span><br><span style="color: hsl(0, 100%, 40%);">-1:</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x2f)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* And enable cache again after setting MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x30)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable MTRR. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_DEF_TYPE_MSR, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- orl $MTRR_DEF_TYPE_EN, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x31)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-__main:</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(POST_PREPARE_RAMSTAGE)</span><br><span style="color: hsl(0, 100%, 40%);">- cld /* Clear direction flag. */</span><br><span style="color: hsl(0, 100%, 40%);">- call romstage_after_car</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Should never see this postcode */</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(POST_DEAD_CODE)</span><br><span> </span><br><span> .Lhlt:</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(POST_DEAD_CODE)</span><br><span> hlt</span><br><span> jmp .Lhlt</span><br><span> </span><br><span>diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c</span><br><span>index dd1fd29..0e1d57e 100644</span><br><span>--- a/src/soc/intel/baytrail/romstage/romstage.c</span><br><span>+++ b/src/soc/intel/baytrail/romstage/romstage.c</span><br><span>@@ -47,7 +47,7 @@</span><br><span> * Because we can't use global variables the stack is used for allocations --</span><br><span> * thus the need to call back and forth. */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void *setup_stack_and_mtrrs(void);</span><br><span style="color: hsl(120, 100%, 40%);">+static void platform_enter_postcar(void);</span><br><span> </span><br><span> static void program_base_addresses(void)</span><br><span> {</span><br><span>@@ -128,7 +128,10 @@</span><br><span> /* Call into mainboard. */</span><br><span> mainboard_romstage_entry(&rp);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- return setup_stack_and_mtrrs();</span><br><span style="color: hsl(120, 100%, 40%);">+ platform_enter_postcar();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* We don't return here */</span><br><span style="color: hsl(120, 100%, 40%);">+ return NULL;</span><br><span> }</span><br><span> </span><br><span> static struct chipset_power_state power_state CAR_GLOBAL;</span><br><span>@@ -245,7 +248,7 @@</span><br><span> </span><br><span> /* setup_stack_and_mtrrs() determines the stack to use after</span><br><span> * cache-as-ram is torn down as well as the MTRR settings to use. */</span><br><span style="color: hsl(0, 100%, 40%);">-static void *setup_stack_and_mtrrs(void)</span><br><span style="color: hsl(120, 100%, 40%);">+static void platform_enter_postcar(void)</span><br><span> {</span><br><span> struct postcar_frame pcf;</span><br><span> uintptr_t top_of_ram;</span><br><span>@@ -267,5 +270,5 @@</span><br><span> postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB,</span><br><span> MTRR_TYPE_WRBACK);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- return postcar_commit_mtrrs(&pcf);</span><br><span style="color: hsl(120, 100%, 40%);">+ run_postcar_phase(&pcf);</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/29930">change 29930</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/29930"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I62a70ae35fe92808f180f2b5f21c5899a96c2c16 </div>
<div style="display:none"> Gerrit-Change-Number: 29930 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-Reviewer: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-Reviewer: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>