<p>Mario Scheithauer has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/29882">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">siemens/mc_apl5: Disable PCI clock outputs on XIO bridges<br><br>On this mainboard there are legacy PCI device, which are connected to<br>different PCIe root ports via PCIe-2-PCI bridges. This patch disables<br>the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges.<br><br>Change-Id: Id36e39c4568f5dd241cd864d2e75365abd0f2a91<br>Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com><br>---<br>M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c<br>1 file changed, 16 insertions(+), 5 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/29882/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c</span><br><span>index 5ad3172..e859380 100644</span><br><span>--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c</span><br><span>@@ -52,11 +52,6 @@</span><br><span>      */</span><br><span>  pcr_write16(PID_ITSS, 0x314c, 0x0321);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-      /* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */</span><br><span style="color: hsl(0, 100%, 40%);">-        dev = dev_find_device(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2001, 0);</span><br><span style="color: hsl(0, 100%, 40%);">-   if (dev)</span><br><span style="color: hsl(0, 100%, 40%);">-                pci_write_config8(dev, 0xd8, 0x3e);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span>  /* Enable CLKRUN_EN for power gating LPC */</span><br><span>  lpc_enable_pci_clk_cntl();</span><br><span> </span><br><span>@@ -82,6 +77,22 @@</span><br><span>          cmd = pci_read_config16(dev, PCI_COMMAND);</span><br><span>           cmd |= PCI_COMMAND_MASTER;</span><br><span>           pci_write_config16(dev, PCI_COMMAND, cmd);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+          /* Disable clock outputs 0-3 (CLKOUT) for upstream XIO2001 PCIe</span><br><span style="color: hsl(120, 100%, 40%);">+                * to PCI Bridge. */</span><br><span style="color: hsl(120, 100%, 40%);">+          struct device *parent = dev->bus->dev;</span><br><span style="color: hsl(120, 100%, 40%);">+          if (parent && parent->device == PCI_DEVICE_ID_TI_XIO2001)</span><br><span style="color: hsl(120, 100%, 40%);">+                  pci_write_config8(parent, 0xd8, 0x0f);</span><br><span style="color: hsl(120, 100%, 40%);">+        }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+   /* Disable clock outputs 1-5 (CLKOUT) for another XIO2001 PCIe to PCI</span><br><span style="color: hsl(120, 100%, 40%);">+  * Bridge on this mainboard.</span><br><span style="color: hsl(120, 100%, 40%);">+   */</span><br><span style="color: hsl(120, 100%, 40%);">+   dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403f, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+      if (dev) {</span><br><span style="color: hsl(120, 100%, 40%);">+            struct device *parent = dev->bus->dev;</span><br><span style="color: hsl(120, 100%, 40%);">+          if (parent && parent->device == PCI_DEVICE_ID_TI_XIO2001)</span><br><span style="color: hsl(120, 100%, 40%);">+                  pci_write_config8(parent, 0xd8, 0x3e);</span><br><span>       }</span><br><span> }</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/29882">change 29882</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/29882"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: Id36e39c4568f5dd241cd864d2e75365abd0f2a91 </div>
<div style="display:none"> Gerrit-Change-Number: 29882 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Mario Scheithauer <mario.scheithauer@siemens.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>