<p>Nico Huber has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/29896">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">util/inteltool: Add Apollo Lake LPC ID and allow to read PCRs<br><br>The P2SB (PCI to Side-Band) bridge is on a different PCI device on APL.<br>Hence, we have to decide based on the LPC ID which device to query.<br><br>Also fix a comment.<br><br>Change-Id: Ie20d7d2d246629d085bcf4740ba28b1e81e6a12a<br>Signed-off-by: Nico Huber <nico.huber@secunet.com><br>---<br>M util/inteltool/inteltool.c<br>M util/inteltool/inteltool.h<br>M util/inteltool/pcr.c<br>3 files changed, 31 insertions(+), 3 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/29896/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c</span><br><span>index d0b4279..6966915 100644</span><br><span>--- a/util/inteltool/inteltool.c</span><br><span>+++ b/util/inteltool/inteltool.c</span><br><span>@@ -247,6 +247,7 @@</span><br><span> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C224, "C224"},</span><br><span> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C226, "C226"},</span><br><span> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H81, "H81"},</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL_LPC, "Apollo Lake" },</span><br><span> /* Intel GPUs */</span><br><span> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_G35_EXPRESS,</span><br><span> "Intel(R) G35 Express Chipset Family" },</span><br><span>diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h</span><br><span>index 5de73aa..f232135 100644</span><br><span>--- a/util/inteltool/inteltool.h</span><br><span>+++ b/util/inteltool/inteltool.h</span><br><span>@@ -227,6 +227,8 @@</span><br><span> #define PCI_DEVICE_ID_INTEL_BAYTRAIL_GFX 0x0f31</span><br><span> #define CPUID_BAYTRAIL 0x30670</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_APL_LPC 0x5ae8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Intel starts counting these generations with the integration of the DRAM controller */</span><br><span> #define PCI_DEVICE_ID_INTEL_CORE_0TH_GEN 0xd132 /* Nehalem */</span><br><span> #define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN 0x0044 /* Westmere */</span><br><span>diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c</span><br><span>index 7223e19..4e75905 100644</span><br><span>--- a/util/inteltool/pcr.c</span><br><span>+++ b/util/inteltool/pcr.c</span><br><span>@@ -70,11 +70,36 @@</span><br><span> {</span><br><span> bool error_exit = false;</span><br><span> bool p2sb_revealed = false;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct pci_dev *p2sb;</span><br><span> </span><br><span> if (sbbar)</span><br><span> return;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- struct pci_dev *const p2sb = pci_get_dev(sb->access, 0, 0, 0x1f, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (sb->device_id) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE:</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVICE_ID_INTEL_H110:</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVICE_ID_INTEL_H170:</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVICE_ID_INTEL_Z170:</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVICE_ID_INTEL_Q170:</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVICE_ID_INTEL_Q150:</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVICE_ID_INTEL_B150:</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVICE_ID_INTEL_C236:</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVICE_ID_INTEL_C232:</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVICE_ID_INTEL_QM170:</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVICE_ID_INTEL_HM170:</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVICE_ID_INTEL_CM236:</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVICE_ID_INTEL_HM175:</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVICE_ID_INTEL_QM175:</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVICE_ID_INTEL_CM238:</span><br><span style="color: hsl(120, 100%, 40%);">+ p2sb = pci_get_dev(sb->access, 0, 0, 0x1f, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVICE_ID_INTEL_APL_LPC:</span><br><span style="color: hsl(120, 100%, 40%);">+ p2sb = pci_get_dev(sb->access, 0, 0, 0x0d, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ perror("Unknown LPC device.");</span><br><span style="color: hsl(120, 100%, 40%);">+ exit(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> </span><br><span> if (!p2sb) {</span><br><span> perror("Can't allocate device node for P2SB.");</span><br><span>@@ -86,8 +111,8 @@</span><br><span> if (p2sb->vendor_id == 0xffff && p2sb->device_id == 0xffff) {</span><br><span> printf("Trying to reveal Primary to Sideband Bridge "</span><br><span> "(P2SB),\nlet's hope the OS doesn't mind... ");</span><br><span style="color: hsl(0, 100%, 40%);">- /* Do not use pci_write_long(). Surrounding</span><br><span style="color: hsl(0, 100%, 40%);">- bytes 0xe0 must be maintained. */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Do not use pci_write_long(). Bytes</span><br><span style="color: hsl(120, 100%, 40%);">+ surrounding 0xe0 must be maintained. */</span><br><span> pci_write_byte(p2sb, 0xe0 + 1, 0);</span><br><span> </span><br><span> pci_fill_info(p2sb, PCI_FILL_IDENT | PCI_FILL_RESCAN);</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/29896">change 29896</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: Ie20d7d2d246629d085bcf4740ba28b1e81e6a12a </div>
<div style="display:none"> Gerrit-Change-Number: 29896 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nico Huber <nico.h@gmx.de> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>