<p>Nico Huber has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/29901">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/apl: Configure LPC serial IRQ mode<br><br>Sync the FSP settings with what coreboot does. Why both FSP and coreboot<br>configure this redundantly stays a secret.<br><br>TEST=Set SERIRQ_CONTINUOUS on kontron/mal10. A CPLD connected to LPC<br>     works correctly now, but was confused by the wrong settings before<br>     because the FSP defaults allowed to disable the LPC clock.<br><br>Change-Id: Id1c7180f460678bf0f9458228591050dd628c052<br>Signed-off-by: Nico Huber <nico.huber@secunet.com><br>---<br>M src/soc/intel/apollolake/chip.c<br>1 file changed, 15 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/29901/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c</span><br><span>index cbd5aba..77b82d4 100644</span><br><span>--- a/src/soc/intel/apollolake/chip.c</span><br><span>+++ b/src/soc/intel/apollolake/chip.c</span><br><span>@@ -610,6 +610,21 @@</span><br><span>   memcpy(silconfig->PcieRpHotPlug, cfg->pcie_rp_hotplug_enable,</span><br><span>         sizeof(silconfig->PcieRpHotPlug));</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+      switch (cfg->serirq_mode) {</span><br><span style="color: hsl(120, 100%, 40%);">+        case SERIRQ_QUIET:</span><br><span style="color: hsl(120, 100%, 40%);">+            silconfig->SirqEnable = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+         silconfig->SirqMode = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+           break;</span><br><span style="color: hsl(120, 100%, 40%);">+        case SERIRQ_CONTINUOUS:</span><br><span style="color: hsl(120, 100%, 40%);">+               silconfig->SirqEnable = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+         silconfig->SirqMode = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+           break;</span><br><span style="color: hsl(120, 100%, 40%);">+        case SERIRQ_OFF:</span><br><span style="color: hsl(120, 100%, 40%);">+      default:</span><br><span style="color: hsl(120, 100%, 40%);">+              silconfig->SirqEnable = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+         break;</span><br><span style="color: hsl(120, 100%, 40%);">+        }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>  if (cfg->emmc_tx_cmd_cntl != 0)</span><br><span>           silconfig->EmmcTxCmdCntl = cfg->emmc_tx_cmd_cntl;</span><br><span>      if (cfg->emmc_tx_data_cntl1 != 0)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/29901">change 29901</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/29901"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: Id1c7180f460678bf0f9458228591050dd628c052 </div>
<div style="display:none"> Gerrit-Change-Number: 29901 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nico Huber <nico.h@gmx.de> </div>
<div style="display:none"> Gerrit-Reviewer: Nico Huber <nico.h@gmx.de> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>