<p>Nico Huber has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/29898">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/common/lpc_lib: Add function to disable LPC Clock Run<br><br>Needed to fix up FSP-S bug on Apollo Lake.<br><br>Change-Id: If09fee07debb1f0de840b0c0bd7a65d338665f7c<br>Signed-off-by: Nico Huber <nico.huber@secunet.com><br>---<br>M src/soc/intel/common/block/include/intelblocks/lpc_lib.h<br>M src/soc/intel/common/block/lpc/lpc_lib.c<br>2 files changed, 7 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/29898/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h</span><br><span>index e7b844f..a600f52 100644</span><br><span>--- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h</span><br><span>+++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h</span><br><span>@@ -97,6 +97,7 @@</span><br><span> void lpc_set_serirq_mode(enum serirq_mode mode);</span><br><span> /* Enable CLKRUN_EN for power gating LPC. */</span><br><span> void lpc_enable_pci_clk_cntl(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void lpc_disable_pci_clkrun(void);</span><br><span> /*</span><br><span> * Setup I/O Decode Range Register for LPC</span><br><span> * ComA Range 3F8h-3FFh [2:0]</span><br><span>diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c</span><br><span>index d27f877..0f26545 100644</span><br><span>--- a/src/soc/intel/common/block/lpc/lpc_lib.c</span><br><span>+++ b/src/soc/intel/common/block/lpc/lpc_lib.c</span><br><span>@@ -301,3 +301,9 @@</span><br><span> {</span><br><span>    pci_write_config8(PCH_DEV_LPC, LPC_PCCTL, LPC_PCCTL_CLKRUN_EN);</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void lpc_disable_pci_clkrun(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+  const u8 pcctl = pci_read_config8(PCH_DEV_LPC, LPC_PCCTL);</span><br><span style="color: hsl(120, 100%, 40%);">+    pci_write_config8(PCH_DEV_LPC, LPC_PCCTL, pcctl & ~LPC_PCCTL_CLKRUN_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/29898">change 29898</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/29898"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: If09fee07debb1f0de840b0c0bd7a65d338665f7c </div>
<div style="display:none"> Gerrit-Change-Number: 29898 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nico Huber <nico.h@gmx.de> </div>
<div style="display:none"> Gerrit-Reviewer: Nico Huber <nico.h@gmx.de> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>