<p>HAOUAS Elyes has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/29847">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src: Remove duplicated round up function<br><br>Fixes 7116ac8037 (src: Make use of 'CEIL_DIV(a, b)' macro across tree).<br><br>Change-Id: I9aabc3fbe7834834c92d6ba59ff0005986622a34<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/commonlib/include/commonlib/helpers.h<br>M src/cpu/allwinner/a10/clock.c<br>M src/cpu/x86/tsc/delay_tsc.c<br>M src/northbridge/intel/gm45/raminit.c<br>M src/northbridge/intel/nehalem/raminit.c<br>M src/northbridge/via/vx900/raminit_ddr3.c<br>M src/soc/nvidia/tegra124/clock.c<br>M src/soc/samsung/exynos5250/cpu.c<br>M src/soc/samsung/exynos5420/clock.c<br>M src/soc/samsung/exynos5420/cpu.c<br>10 files changed, 25 insertions(+), 27 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/29847/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h</span><br><span>index f2acedc..03f4306 100644</span><br><span>--- a/src/commonlib/include/commonlib/helpers.h</span><br><span>+++ b/src/commonlib/include/commonlib/helpers.h</span><br><span>@@ -36,7 +36,6 @@</span><br><span> #define MAX(a, b) ((a) > (b) ? (a) : (b))</span><br><span> #endif</span><br><span> #define ABS(a) (((a) < 0) ? (-(a)) : (a))</span><br><span style="color: hsl(0, 100%, 40%);">-#define CEIL_DIV(a, b) (((a) + (b) - 1) / (b))</span><br><span> #define IS_POWER_OF_2(x) (((x) & ((x) - 1)) == 0)</span><br><span> #define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y))</span><br><span> /*</span><br><span>diff --git a/src/cpu/allwinner/a10/clock.c b/src/cpu/allwinner/a10/clock.c</span><br><span>index ae50e06..7ea5424 100644</span><br><span>--- a/src/cpu/allwinner/a10/clock.c</span><br><span>+++ b/src/cpu/allwinner/a10/clock.c</span><br><span>@@ -247,8 +247,8 @@</span><br><span> * will always be in spec, as long as AHB is in spec, although the max</span><br><span> * AHB0 clock we can get is 125 MHz</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">- axi = CEIL_DIV(actual_mhz, 450); /* Max 450 MHz */</span><br><span style="color: hsl(0, 100%, 40%);">- ahb = CEIL_DIV(actual_mhz/axi, 250); /* Max 250 MHz */</span><br><span style="color: hsl(120, 100%, 40%);">+ axi = DIV_ROUND_UP(actual_mhz, 450); /* Max 450 MHz */</span><br><span style="color: hsl(120, 100%, 40%);">+ ahb = DIV_ROUND_UP(actual_mhz/axi, 250); /* Max 250 MHz */</span><br><span> apb0 = 2; /* Max 150 MHz */</span><br><span> </span><br><span> ahb_exp = log2_ceil(ahb);</span><br><span>diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c</span><br><span>index 04f709f..a589cdb 100644</span><br><span>--- a/src/cpu/x86/tsc/delay_tsc.c</span><br><span>+++ b/src/cpu/x86/tsc/delay_tsc.c</span><br><span>@@ -83,7 +83,7 @@</span><br><span> if (end.lo <= CALIBRATE_DIVISOR)</span><br><span> goto bad_ctc;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- return CEIL_DIV(end.lo, CALIBRATE_DIVISOR);</span><br><span style="color: hsl(120, 100%, 40%);">+ return DIV_ROUND_UP(end.lo, CALIBRATE_DIVISOR);</span><br><span> }</span><br><span> </span><br><span> /*</span><br><span>diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c</span><br><span>index d067dc2..ddf705f 100644</span><br><span>--- a/src/northbridge/intel/gm45/raminit.c</span><br><span>+++ b/src/northbridge/intel/gm45/raminit.c</span><br><span>@@ -361,8 +361,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define ROUNDUP_DIV(val, by) CEIL_DIV(val, by)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ROUNDUP_DIV_THIS(val, by) val = ROUNDUP_DIV(val, by)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ROUNDUP_DIV_THIS(val, by) (val = DIV_ROUND_UP(val, by))</span><br><span> static fsb_clock_t read_fsb_clock(void)</span><br><span> {</span><br><span> switch (MCHBAR32(CLKCFG_MCHBAR) & CLKCFG_FSBCLK_MASK) {</span><br><span>diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c</span><br><span>index d0dfb75..54ef278 100644</span><br><span>--- a/src/northbridge/intel/nehalem/raminit.c</span><br><span>+++ b/src/northbridge/intel/nehalem/raminit.c</span><br><span>@@ -602,7 +602,7 @@</span><br><span> break;</span><br><span> }</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- min_cas_latency = CEIL_DIV(cas_latency_time, cycletime);</span><br><span style="color: hsl(120, 100%, 40%);">+ min_cas_latency = DIV_ROUND_UP(cas_latency_time, cycletime);</span><br><span> cas_latency = 0;</span><br><span> while (supported_cas_latencies) {</span><br><span> cas_latency = find_highest_bit_set(supported_cas_latencies) + 3;</span><br><span>@@ -3231,7 +3231,7 @@</span><br><span> </span><br><span> static inline int div_roundup(int a, int b)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- return CEIL_DIV(a, b);</span><br><span style="color: hsl(120, 100%, 40%);">+ return DIV_ROUND_UP(a, b);</span><br><span> }</span><br><span> </span><br><span> static unsigned lcm(unsigned a, unsigned b)</span><br><span>diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c</span><br><span>index 1d05fa7..7acab31 100644</span><br><span>--- a/src/northbridge/via/vx900/raminit_ddr3.c</span><br><span>+++ b/src/northbridge/via/vx900/raminit_ddr3.c</span><br><span>@@ -572,7 +572,7 @@</span><br><span> printram("Selected DRAM frequency: %u MHz\n", val32);</span><br><span> </span><br><span> /* Find CAS and CWL latencies */</span><br><span style="color: hsl(0, 100%, 40%);">- val = CEIL_DIV(ctrl->tAA, ctrl->tCK);</span><br><span style="color: hsl(120, 100%, 40%);">+ val = DIV_ROUND_UP(ctrl->tAA, ctrl->tCK);</span><br><span> printram("Minimum CAS latency : %uT\n", val);</span><br><span> /* Find lowest supported CAS latency that satisfies the minimum value */</span><br><span> while (!((ctrl->cas_supported >> (val - 4)) & 1)</span><br><span>@@ -591,30 +591,30 @@</span><br><span> pci_write_config8(MCU, 0xc0, reg8);</span><br><span> </span><br><span> /* Find tRCD */</span><br><span style="color: hsl(0, 100%, 40%);">- val = CEIL_DIV(ctrl->tRCD, ctrl->tCK);</span><br><span style="color: hsl(120, 100%, 40%);">+ val = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK);</span><br><span> printram("Selected tRCD : %uT\n", val);</span><br><span> reg8 = ((val - 4) & 0x7) << 4;</span><br><span> /* Find tRP */</span><br><span style="color: hsl(0, 100%, 40%);">- val = CEIL_DIV(ctrl->tRP, ctrl->tCK);</span><br><span style="color: hsl(120, 100%, 40%);">+ val = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK);</span><br><span> printram("Selected tRP : %uT\n", val);</span><br><span> reg8 |= ((val - 4) & 0x7);</span><br><span> pci_write_config8(MCU, 0xc1, reg8);</span><br><span> </span><br><span> /* Find tRAS */</span><br><span style="color: hsl(0, 100%, 40%);">- val = CEIL_DIV(ctrl->tRAS, ctrl->tCK);</span><br><span style="color: hsl(120, 100%, 40%);">+ val = DIV_ROUND_UP(ctrl->tRAS, ctrl->tCK);</span><br><span> printram("Selected tRAS : %uT\n", val);</span><br><span> reg8 = ((val - 15) & 0x7) << 4;</span><br><span> /* Find tWR */</span><br><span style="color: hsl(0, 100%, 40%);">- ctrl->WR = CEIL_DIV(ctrl->tWR, ctrl->tCK);</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrl->WR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK);</span><br><span> printram("Selected tWR : %uT\n", ctrl->WR);</span><br><span> reg8 |= ((ctrl->WR - 4) & 0x7);</span><br><span> pci_write_config8(MCU, 0xc2, reg8);</span><br><span> </span><br><span> /* Find tFAW */</span><br><span style="color: hsl(0, 100%, 40%);">- tFAW = CEIL_DIV(ctrl->tFAW, ctrl->tCK);</span><br><span style="color: hsl(120, 100%, 40%);">+ tFAW = DIV_ROUND_UP(ctrl->tFAW, ctrl->tCK);</span><br><span> printram("Selected tFAW : %uT\n", tFAW);</span><br><span> /* Find tRRD */</span><br><span style="color: hsl(0, 100%, 40%);">- tRRD = CEIL_DIV(ctrl->tRRD, ctrl->tCK);</span><br><span style="color: hsl(120, 100%, 40%);">+ tRRD = DIV_ROUND_UP(ctrl->tRRD, ctrl->tCK);</span><br><span> printram("Selected tRRD : %uT\n", tRRD);</span><br><span> val = tFAW - 4 * tRRD; /* number of cycles above 4*tRRD */</span><br><span> reg8 = ((val - 0) & 0x7) << 4;</span><br><span>@@ -622,11 +622,11 @@</span><br><span> pci_write_config8(MCU, 0xc3, reg8);</span><br><span> </span><br><span> /* Find tRTP */</span><br><span style="color: hsl(0, 100%, 40%);">- val = CEIL_DIV(ctrl->tRTP, ctrl->tCK);</span><br><span style="color: hsl(120, 100%, 40%);">+ val = DIV_ROUND_UP(ctrl->tRTP, ctrl->tCK);</span><br><span> printram("Selected tRTP : %uT\n", val);</span><br><span> reg8 = ((val & 0x3) << 4);</span><br><span> /* Find tWTR */</span><br><span style="color: hsl(0, 100%, 40%);">- val = CEIL_DIV(ctrl->tWTR, ctrl->tCK);</span><br><span style="color: hsl(120, 100%, 40%);">+ val = DIV_ROUND_UP(ctrl->tWTR, ctrl->tCK);</span><br><span> printram("Selected tWTR : %uT\n", val);</span><br><span> reg8 |= ((val - 2) & 0x7);</span><br><span> pci_mod_config8(MCU, 0xc4, 0x3f, reg8);</span><br><span>@@ -639,7 +639,7 @@</span><br><span> * Since we previously set RxC4[7]</span><br><span> */</span><br><span> reg8 = pci_read_config8(MCU, 0xc5);</span><br><span style="color: hsl(0, 100%, 40%);">- val = CEIL_DIV(ctrl->tRFC, ctrl->tCK);</span><br><span style="color: hsl(120, 100%, 40%);">+ val = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK);</span><br><span> printram("Minimum tRFC : %uT\n", val);</span><br><span> if (val < 30) {</span><br><span> val = 0;</span><br><span>@@ -652,7 +652,7 @@</span><br><span> pci_write_config8(MCU, 0xc5, reg8);</span><br><span> </span><br><span> /* Where does this go??? */</span><br><span style="color: hsl(0, 100%, 40%);">- val = CEIL_DIV(ctrl->tRC, ctrl->tCK);</span><br><span style="color: hsl(120, 100%, 40%);">+ val = DIV_ROUND_UP(ctrl->tRC, ctrl->tCK);</span><br><span> printram("Required tRC : %uT\n", val);</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c</span><br><span>index 9173e62..b9a4cd1 100644</span><br><span>--- a/src/soc/nvidia/tegra124/clock.c</span><br><span>+++ b/src/soc/nvidia/tegra124/clock.c</span><br><span>@@ -247,17 +247,17 @@</span><br><span> 1 << 8); /* (rst) phy_divm */</span><br><span> </span><br><span> write32(&clk_rst->utmip_pll_cfg1,</span><br><span style="color: hsl(0, 100%, 40%);">- CEIL_DIV(khz, 8000) << 27 | /* pllu_enbl_cnt / 8 (1us) */</span><br><span style="color: hsl(120, 100%, 40%);">+ DIV_ROUND_UP(khz, 8000) << 27 | /* pllu_enbl_cnt / 8 (1us) */</span><br><span> 0 << 16 | /* PLLU pwrdn */</span><br><span> 0 << 14 | /* pll_enable pwrdn */</span><br><span> 0 << 12 | /* pll_active pwrdn */</span><br><span style="color: hsl(0, 100%, 40%);">- CEIL_DIV(khz, 102) << 0); /* phy_stbl_cnt / 256 (2.5ms) */</span><br><span style="color: hsl(120, 100%, 40%);">+ DIV_ROUND_UP(khz, 102) << 0); /* phy_stbl_cnt / 256 (2.5ms) */</span><br><span> </span><br><span> /* TODO: TRM can't decide if actv is 5us or 10us, keep an eye on it */</span><br><span> write32(&clk_rst->utmip_pll_cfg2,</span><br><span> 0 << 24 | /* SAMP_D/XDEV pwrdn */</span><br><span style="color: hsl(0, 100%, 40%);">- CEIL_DIV(khz, 3200) << 18 | /* phy_actv_cnt / 16 (5us) */</span><br><span style="color: hsl(0, 100%, 40%);">- CEIL_DIV(khz, 256) << 6 | /* pllu_stbl_cnt / 256 (1ms) */</span><br><span style="color: hsl(120, 100%, 40%);">+ DIV_ROUND_UP(khz, 3200) << 18 | /* phy_actv_cnt / 16 (5us) */</span><br><span style="color: hsl(120, 100%, 40%);">+ DIV_ROUND_UP(khz, 256) << 6 | /* pllu_stbl_cnt / 256 (1ms) */</span><br><span> 0 << 4 | /* SAMP_C/USB3 pwrdn */</span><br><span> 0 << 2 | /* SAMP_B/XHOST pwrdn */</span><br><span> 0 << 0); /* SAMP_A/USBD pwrdn */</span><br><span>diff --git a/src/soc/samsung/exynos5250/cpu.c b/src/soc/samsung/exynos5250/cpu.c</span><br><span>index aed1114..4fdb8f8 100644</span><br><span>--- a/src/soc/samsung/exynos5250/cpu.c</span><br><span>+++ b/src/soc/samsung/exynos5250/cpu.c</span><br><span>@@ -112,7 +112,7 @@</span><br><span> u32 lcdbase = get_fb_base_kb() * KiB;</span><br><span> </span><br><span> ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB - FB_SIZE_KB);</span><br><span style="color: hsl(0, 100%, 40%);">- mmio_resource(dev, 1, lcdbase / KiB, CEIL_DIV(fb_size, KiB));</span><br><span style="color: hsl(120, 100%, 40%);">+ mmio_resource(dev, 1, lcdbase / KiB, DIV_ROUND_UP(fb_size, KiB));</span><br><span> </span><br><span> exynos_displayport_init(dev, lcdbase, fb_size);</span><br><span> </span><br><span>diff --git a/src/soc/samsung/exynos5420/clock.c b/src/soc/samsung/exynos5420/clock.c</span><br><span>index 04125d9..0da3522 100644</span><br><span>--- a/src/soc/samsung/exynos5420/clock.c</span><br><span>+++ b/src/soc/samsung/exynos5420/clock.c</span><br><span>@@ -345,7 +345,7 @@</span><br><span> }</span><br><span> printk(BIOS_DEBUG, "%s(%d): sdclkin: %ld\n", __func__, device_index, sdclkin);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- cclkin = CEIL_DIV(sdclkin, freq);</span><br><span style="color: hsl(120, 100%, 40%);">+ cclkin = DIV_ROUND_UP(sdclkin, freq);</span><br><span> set_mmc_clk(device_index, cclkin);</span><br><span> return 0;</span><br><span> }</span><br><span>diff --git a/src/soc/samsung/exynos5420/cpu.c b/src/soc/samsung/exynos5420/cpu.c</span><br><span>index ecda54b..fa4cd06 100644</span><br><span>--- a/src/soc/samsung/exynos5420/cpu.c</span><br><span>+++ b/src/soc/samsung/exynos5420/cpu.c</span><br><span>@@ -114,7 +114,7 @@</span><br><span> dcache_clean_invalidate_by_mva((void *)lower, upper - lower);</span><br><span> mmu_config_range(lower / MiB, (upper - lower) / MiB, DCACHE_OFF);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- mmio_resource(dev, 1, lcdbase/KiB, CEIL_DIV(fb_size, KiB));</span><br><span style="color: hsl(120, 100%, 40%);">+ mmio_resource(dev, 1, lcdbase/KiB, DIV_ROUND_UP(fb_size, KiB));</span><br><span> }</span><br><span> </span><br><span> static void tps65090_thru_ec_fet_disable(int index)</span><br><span>@@ -134,7 +134,7 @@</span><br><span> u32 lcdbase = get_fb_base_kb() * KiB;</span><br><span> </span><br><span> ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB - FB_SIZE_KB);</span><br><span style="color: hsl(0, 100%, 40%);">- mmio_resource(dev, 1, lcdbase / KiB, CEIL_DIV(fb_size, KiB));</span><br><span style="color: hsl(120, 100%, 40%);">+ mmio_resource(dev, 1, lcdbase / KiB, DIV_ROUND_UP(fb_size, KiB));</span><br><span> </span><br><span> /*</span><br><span> * Disable LCD FETs before we do anything with the display.</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/29847">change 29847</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/29847"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I9aabc3fbe7834834c92d6ba59ff0005986622a34 </div>
<div style="display:none"> Gerrit-Change-Number: 29847 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: HAOUAS Elyes <ehaouas@noos.fr> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>