<p>Patrick Georgi has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/29814">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/apollolake: use a named choice for power settings<br><br>This prevents illegal configurations.<br><br>Change-Id: I88598c5e32fc48d04f7c1e987a0b2549a87da8f2<br>Signed-off-by: Patrick Georgi <pgeorgi@google.com><br>---<br>M src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig<br>M src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig<br>M src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig<br>M src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig<br>M src/soc/intel/apollolake/Kconfig<br>5 files changed, 34 insertions(+), 17 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/29814/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig</span><br><span>index 76d62fc..e2922f7 100644</span><br><span>--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig</span><br><span>@@ -7,6 +7,9 @@</span><br><span> select DRIVERS_I2C_RX6110SA</span><br><span> select DRIVER_SIEMENS_NC_FPGA</span><br><span> select NC_FPGA_NOTIFY_CB_READY</span><br><span style="color: hsl(0, 100%, 40%);">- select APL_SKIP_SET_POWER_LIMITS</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+choice APL_POWER_SETTING</span><br><span style="color: hsl(120, 100%, 40%);">+ default APL_SKIP_SET_POWER_LIMITS</span><br><span style="color: hsl(120, 100%, 40%);">+endchoice</span><br><span> </span><br><span> endif # BOARD_SIEMENS_MC_APL1</span><br><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig</span><br><span>index 32db935..811a21e 100644</span><br><span>--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig</span><br><span>@@ -7,6 +7,9 @@</span><br><span> select DRIVERS_I2C_RX6110SA</span><br><span> select DRIVER_SIEMENS_NC_FPGA</span><br><span> select NC_FPGA_NOTIFY_CB_READY</span><br><span style="color: hsl(0, 100%, 40%);">- select APL_SKIP_SET_POWER_LIMITS</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+choice APL_POWER_SETTING</span><br><span style="color: hsl(120, 100%, 40%);">+ default APL_SKIP_SET_POWER_LIMITS</span><br><span style="color: hsl(120, 100%, 40%);">+endchoice</span><br><span> </span><br><span> endif # BOARD_SIEMENS_MC_APL3</span><br><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig</span><br><span>index 925b04f..19dfeab 100644</span><br><span>--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig</span><br><span>@@ -4,6 +4,9 @@</span><br><span> config BOARD_SPECIFIC_OPTIONS</span><br><span> def_bool y</span><br><span> select DRIVER_INTEL_I210</span><br><span style="color: hsl(0, 100%, 40%);">- select APL_SET_MIN_CLOCK_RATIO</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+choice APL_POWER_SETTING</span><br><span style="color: hsl(120, 100%, 40%);">+ default APL_SET_MIN_CLOCK_RATIO</span><br><span style="color: hsl(120, 100%, 40%);">+endchoice</span><br><span> </span><br><span> endif # BOARD_SIEMENS_MC_APL4</span><br><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig</span><br><span>index 196176c..0f6d1f5 100644</span><br><span>--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig</span><br><span>@@ -7,6 +7,9 @@</span><br><span> select DRIVERS_I2C_RX6110SA</span><br><span> select DRIVER_SIEMENS_NC_FPGA</span><br><span> select NC_FPGA_NOTIFY_CB_READY</span><br><span style="color: hsl(0, 100%, 40%);">- select APL_SKIP_SET_POWER_LIMITS</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+choice APL_POWER_SETTING</span><br><span style="color: hsl(120, 100%, 40%);">+ default APL_SKIP_SET_POWER_LIMITS</span><br><span style="color: hsl(120, 100%, 40%);">+endchoice</span><br><span> </span><br><span> endif # BOARD_SIEMENS_MC_APL5</span><br><span>diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig</span><br><span>index 4a841be..5c50f6e 100644</span><br><span>--- a/src/soc/intel/apollolake/Kconfig</span><br><span>+++ b/src/soc/intel/apollolake/Kconfig</span><br><span>@@ -368,24 +368,29 @@</span><br><span> int</span><br><span> default 100</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+choice APL_POWER_SETTING</span><br><span style="color: hsl(120, 100%, 40%);">+ prompt "Power configuration"</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ Apollo Lake's power management can be configured in multiple ways:</span><br><span style="color: hsl(120, 100%, 40%);">+ By default the Running Average Power Limits (RAPL) algorithm can</span><br><span style="color: hsl(120, 100%, 40%);">+ setup power management reasonably.</span><br><span style="color: hsl(120, 100%, 40%);">+ Some hardware can also run without these limits, while for other,</span><br><span style="color: hsl(120, 100%, 40%);">+ the minimum CPU clock might be preferable as a default.</span><br><span style="color: hsl(120, 100%, 40%);">+ The OS can still override the configuration with a p-state driver.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config APL_DEFAULT_POWER_LIMITS</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ prompt "Use default RAPL algorithm"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config APL_SKIP_SET_POWER_LIMITS</span><br><span> bool</span><br><span style="color: hsl(0, 100%, 40%);">- default n</span><br><span style="color: hsl(0, 100%, 40%);">- help</span><br><span style="color: hsl(0, 100%, 40%);">- Some Apollo Lake mainboards do not need the Running Average Power</span><br><span style="color: hsl(0, 100%, 40%);">- Limits (RAPL) algorithm for a constant power management.</span><br><span style="color: hsl(0, 100%, 40%);">- Set this config option to skip the RAPL configuration.</span><br><span style="color: hsl(120, 100%, 40%);">+ prompt "Skip RAPL configuration"</span><br><span> </span><br><span> config APL_SET_MIN_CLOCK_RATIO</span><br><span> bool</span><br><span style="color: hsl(0, 100%, 40%);">- depends on !APL_SKIP_SET_POWER_LIMITS</span><br><span style="color: hsl(0, 100%, 40%);">- default n</span><br><span style="color: hsl(0, 100%, 40%);">- help</span><br><span style="color: hsl(0, 100%, 40%);">- If the power budget of the mainboard is limited, it can be useful to</span><br><span style="color: hsl(0, 100%, 40%);">- limit the CPU power dissipation at the cost of performance by setting</span><br><span style="color: hsl(0, 100%, 40%);">- the lowest possible CPU clock. Enable this option if you need smallest</span><br><span style="color: hsl(0, 100%, 40%);">- possible CPU clock. This setting can be overruled by the OS if it has an</span><br><span style="color: hsl(0, 100%, 40%);">- p-state driver which can adjust the clock to its need.</span><br><span style="color: hsl(120, 100%, 40%);">+ prompt "Set clock ratio to the minimum possible"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endchoice</span><br><span> </span><br><span> # M and N divisor values for clock frequency configuration.</span><br><span> # These values get us a 1.836 MHz clock (ideally we want 1.843 MHz)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/29814">change 29814</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/29814"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I88598c5e32fc48d04f7c1e987a0b2549a87da8f2 </div>
<div style="display:none"> Gerrit-Change-Number: 29814 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>