<p>PraveenX Hodagatta Pranesh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/29808">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Add device settings for PL4 power limit<br><br>PL4 is a preemptive CPU package peak power limit,it will never be exceeded.<br>Power is preemptively lowered before limit is reached.<br><br>This change provides option in devicetree and feeds FSP PowerLimit4 UPD for<br>power limit purpose.<br><br>Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com><br>Change-Id: I64b5a029104a102e5741e8b37c7992f2693180e8<br>---<br>M src/soc/intel/skylake/chip.h<br>M src/soc/intel/skylake/chip_fsp20.c<br>2 files changed, 4 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/29808/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h</span><br><span>index b1ffcb2..21dddd4 100644</span><br><span>--- a/src/soc/intel/skylake/chip.h</span><br><span>+++ b/src/soc/intel/skylake/chip.h</span><br><span>@@ -97,6 +97,9 @@</span><br><span>  /* TCC activation offset */</span><br><span>  int tcc_offset;</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+   /* Power Limit Related */</span><br><span style="color: hsl(120, 100%, 40%);">+     u32 PowerLimit4;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>   /* PL2 Override value in Watts */</span><br><span>    u32 tdp_pl2_override;</span><br><span>        /* PL1 Override value in Watts */</span><br><span>diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c</span><br><span>index 8a78348..18c2aef 100644</span><br><span>--- a/src/soc/intel/skylake/chip_fsp20.c</span><br><span>+++ b/src/soc/intel/skylake/chip_fsp20.c</span><br><span>@@ -369,6 +369,7 @@</span><br><span> </span><br><span>     tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi;</span><br><span>       tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock;</span><br><span style="color: hsl(120, 100%, 40%);">+    tconfig->PowerLimit4 = config->PowerLimit4;</span><br><span>    /*</span><br><span>    * To disable HECI, the Psf needs to be left unlocked</span><br><span>         * by FSP till end of post sequence. Based on the devicetree</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/29808">change 29808</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/29808"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I64b5a029104a102e5741e8b37c7992f2693180e8 </div>
<div style="display:none"> Gerrit-Change-Number: 29808 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>