<p>Patrick Georgi <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/c/coreboot/+/29687">View Change</a></p><div style="white-space:pre-wrap">Approvals:
  build bot (Jenkins): Verified
  Huang Jin: Looks good to me, approved

</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">drivers/intel/fsp1_1/cache_as_ram.inc: Dont include soc/car_setup.S<br><br>soc/car_setup.S is included when SKIP_FSP_CAR is enabled,<br>but no chipset/SoC have car_setup.S available.<br>Remove include and post_code() call always solving build errors.<br><br>BUG=NA<br>TEST=NA<br><br>Change-Id: Iebae2940eb10c9ca9054437be4740c79137bcc61<br>Signed-off-by: Frans Hendriks <fhendriks@eltan.com><br>Reviewed-on: https://review.coreboot.org/c/29687<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Huang Jin <huang.jin@intel.com><br>---<br>M src/drivers/intel/fsp1_1/cache_as_ram.inc<br>1 file changed, 0 insertions(+), 13 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc</span><br><span>index af6f3a9..934ae67 100644</span><br><span>--- a/src/drivers/intel/fsp1_1/cache_as_ram.inc</span><br><span>+++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc</span><br><span>@@ -37,19 +37,6 @@</span><br><span> cache_as_ram:</span><br><span>     post_code(0x20)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if IS_ENABLED(CONFIG_SKIP_FSP_CAR)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-  /*</span><br><span style="color: hsl(0, 100%, 40%);">-       * SOC specific setup</span><br><span style="color: hsl(0, 100%, 40%);">-    * NOTE: This has to preserve the registers</span><br><span style="color: hsl(0, 100%, 40%);">-      * mm0, mm1 and edi.</span><br><span style="color: hsl(0, 100%, 40%);">-     */</span><br><span style="color: hsl(0, 100%, 40%);">-     #include <soc/car_setup.S></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-        post_code(0x28)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span>        /*</span><br><span>    * Find the FSP binary in cbfs.</span><br><span>       * Make a fake stack that has the return value back to this code.</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/29687">change 29687</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/29687"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: Iebae2940eb10c9ca9054437be4740c79137bcc61 </div>
<div style="display:none"> Gerrit-Change-Number: 29687 </div>
<div style="display:none"> Gerrit-PatchSet: 2 </div>
<div style="display:none"> Gerrit-Owner: Frans Hendriks <fhendriks@eltan.com> </div>
<div style="display:none"> Gerrit-Reviewer: Frans Hendriks <fhendriks@eltan.com> </div>
<div style="display:none"> Gerrit-Reviewer: Huang Jin <huang.jin@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: York Yang <york.yang@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-MessageType: merged </div>