<p>Werner Zeh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/29798">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">intelblocks/cpu: Fix wrong comment for P_Req field in PERF_CTL MSR<br><br>The mentioned bits 14:8 are wrong as the functions always write<br>bits 15:8. What happens is visible in the written code. There is no need<br>for an extra comment.<br><br>Change-Id: I59b4d24d01a0a8fa74912f9754e7bbb217ca269d<br>Signed-off-by: Werner Zeh <werner.zeh@siemens.com><br>---<br>M src/soc/intel/common/block/cpu/cpulib.c<br>M src/soc/intel/common/block/include/intelblocks/cpulib.h<br>2 files changed, 10 insertions(+), 10 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/29798/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c</span><br><span>index f2142d9..d18b50c 100644</span><br><span>--- a/src/soc/intel/common/block/cpu/cpulib.c</span><br><span>+++ b/src/soc/intel/common/block/cpu/cpulib.c</span><br><span>@@ -34,7 +34,7 @@</span><br><span> #include <stdint.h></span><br><span> </span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set PERF_CTL MSR (0x199) P_Req with</span><br><span>  * Turbo Ratio which is the Maximum Ratio.</span><br><span>  */</span><br><span> void cpu_set_max_ratio(void)</span><br><span>@@ -86,7 +86,7 @@</span><br><span>  * 23:16 -    MAX_TURBO_3_CORES</span><br><span>  * 31:24 - MAX_TURBO_4_CORES</span><br><span>  *</span><br><span style="color: hsl(0, 100%, 40%);">- * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with that value.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set PERF_CTL MSR (0x199) P_Req with that value.</span><br><span>  */</span><br><span> void cpu_set_p_state_to_turbo_ratio(void)</span><br><span> {</span><br><span>@@ -106,7 +106,7 @@</span><br><span>  * TDP level ratio to be used for specific processor (in units</span><br><span>  * of 100MHz).</span><br><span>  *</span><br><span style="color: hsl(0, 100%, 40%);">- * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with that value.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set PERF_CTL MSR (0x199) P_Req with that value.</span><br><span>  */</span><br><span> void cpu_set_p_state_to_nominal_tdp_ratio(void)</span><br><span> {</span><br><span>@@ -125,7 +125,7 @@</span><br><span>  * PLATFORM_INFO MSR (0xCE) Bits 15:8 tells</span><br><span>  * MAX_NON_TURBO_LIM_RATIO.</span><br><span>  *</span><br><span style="color: hsl(0, 100%, 40%);">- * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with that value.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set PERF_CTL MSR (0x199) P_Req with that value.</span><br><span>  */</span><br><span> void cpu_set_p_state_to_max_non_turbo_ratio(void)</span><br><span> {</span><br><span>@@ -142,7 +142,7 @@</span><br><span> }</span><br><span> </span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with the value</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set PERF_CTL MSR (0x199) P_Req with the value</span><br><span>  * for maximum efficiency. This value is reported in PLATFORM_INFO MSR (0xCE)</span><br><span>  * in Bits 47:40 and is extracted with cpu_get_min_ratio().</span><br><span>  */</span><br><span>diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h</span><br><span>index 0d51146..5cea96e 100644</span><br><span>--- a/src/soc/intel/common/block/include/intelblocks/cpulib.h</span><br><span>+++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h</span><br><span>@@ -20,7 +20,7 @@</span><br><span> #include <stdint.h></span><br><span> </span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set PERF_CTL MSR (0x199) P_Req with</span><br><span>  * Turbo Ratio which is the Maximum Ratio.</span><br><span>  */</span><br><span> void cpu_set_max_ratio(void);</span><br><span>@@ -52,7 +52,7 @@</span><br><span>  * 23:16 -        MAX_TURBO_3_CORES</span><br><span>  * 31:24 - MAX_TURBO_4_CORES</span><br><span>  *</span><br><span style="color: hsl(0, 100%, 40%);">- * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with that value.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set PERF_CTL MSR (0x199) P_Req with that value.</span><br><span>  */</span><br><span> void cpu_set_p_state_to_turbo_ratio(void);</span><br><span> </span><br><span>@@ -61,7 +61,7 @@</span><br><span>  * TDP level ratio to be used for specific processor (in units</span><br><span>  * of 100MHz).</span><br><span>  *</span><br><span style="color: hsl(0, 100%, 40%);">- * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with that value.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set PERF_CTL MSR (0x199) P_Req with that value.</span><br><span>  */</span><br><span> void cpu_set_p_state_to_nominal_tdp_ratio(void);</span><br><span> </span><br><span>@@ -69,12 +69,12 @@</span><br><span>  * PLATFORM_INFO MSR (0xCE) Bits 15:8 tells</span><br><span>  * MAX_NON_TURBO_LIM_RATIO.</span><br><span>  *</span><br><span style="color: hsl(0, 100%, 40%);">- * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with that value.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set PERF_CTL MSR (0x199) P_Req with that value.</span><br><span>  */</span><br><span> void cpu_set_p_state_to_max_non_turbo_ratio(void);</span><br><span> </span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with the value</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set PERF_CTL MSR (0x199) P_Req with the value</span><br><span>  * for maximum efficiency. This value is reported in PLATFORM_INFO MSR (0xCE)</span><br><span>  * in Bits 47:40 and is extracted with cpu_get_min_ratio().</span><br><span>  */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/29798">change 29798</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/29798"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I59b4d24d01a0a8fa74912f9754e7bbb217ca269d </div>
<div style="display:none"> Gerrit-Change-Number: 29798 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Werner Zeh <werner.zeh@siemens.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>