<p>Jenny Tc has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/29775">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">SMI: Introduce CONFIG_SOC_INTEL_BYPASS_PORT_B2_SMI<br><br>With Lazy SCI mask, EC and OS can take over iniitializing the SCI<br>events done by B2_SMI interrupt.<br><br>Change-Id: I43ca93972fa4d870632707cb9a9e74ab80cbd5d5<br>Signed-off-by: Jenny TC <jenny.tc@intel.com><br>---<br>M src/ec/google/chromeec/smihandler.c<br>M src/soc/intel/common/Kconfig<br>2 files changed, 8 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/29775/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/ec/google/chromeec/smihandler.c b/src/ec/google/chromeec/smihandler.c</span><br><span>index cab7192..d608db5 100644</span><br><span>--- a/src/ec/google/chromeec/smihandler.c</span><br><span>+++ b/src/ec/google/chromeec/smihandler.c</span><br><span>@@ -99,6 +99,7 @@</span><br><span>       google_chromeec_get_device_current_events();</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_SOC_INTEL_BYPASS_PORT_B2_SMI)</span><br><span> void chromeec_smi_apmc(int apmc, uint64_t sci_mask, uint64_t smi_mask)</span><br><span> {</span><br><span>    switch (apmc) {</span><br><span>@@ -114,3 +115,6 @@</span><br><span>                break;</span><br><span>       }</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+void chromeec_smi_apmc(int apmc, uint64_t sci_mask, uint64_t smi_mask) { }</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig</span><br><span>index 27d3f59..9097195 100644</span><br><span>--- a/src/soc/intel/common/Kconfig</span><br><span>+++ b/src/soc/intel/common/Kconfig</span><br><span>@@ -65,6 +65,10 @@</span><br><span>  bool</span><br><span>         default n</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config SOC_INTEL_BYPASS_PORT_B2_SMI</span><br><span style="color: hsl(120, 100%, 40%);">+        bool</span><br><span style="color: hsl(120, 100%, 40%);">+      default n</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config TPM_TIS_ACPI_INTERRUPT</span><br><span>         int</span><br><span>  help</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/29775">change 29775</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/29775"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I43ca93972fa4d870632707cb9a9e74ab80cbd5d5 </div>
<div style="display:none"> Gerrit-Change-Number: 29775 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Jenny Tc <jenny.tc@intel.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>