<p>Duncan Laurie <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/c/coreboot/+/29671">View Change</a></p><div style="white-space:pre-wrap">Approvals:
  build bot (Jenkins): Verified
  Lijian Zhao: Looks good to me, approved

</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Fix IO decode setup<br><br>This change makes the early IO decode setup mirror that of other<br>Intel SOCs and fixes issues with COM1 not being enabled properly.<br><br>Tested by successfully successfully receiving serial output from<br>an 8250IO UART device at the standard 0x3f8 base address.<br><br>Change-Id: I9bd894fea62b78b81e5c80b5e88a539ebddac2df<br>Signed-off-by: Duncan Laurie <dlaurie@google.com><br>Reviewed-on: https://review.coreboot.org/c/29671<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/soc/intel/cannonlake/bootblock/pch.c<br>1 file changed, 29 insertions(+), 11 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c</span><br><span>index 3ef084a..b06c81b 100644</span><br><span>--- a/src/soc/intel/cannonlake/bootblock/pch.c</span><br><span>+++ b/src/soc/intel/cannonlake/bootblock/pch.c</span><br><span>@@ -46,6 +46,9 @@</span><br><span> #define PCR_PSFX_TO_SHDW_PCIEN_IOEN   0x01</span><br><span> #define PCR_PSFX_T0_SHDW_PCIEN  0x1C</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_DMI_DMICTL                0x2234</span><br><span style="color: hsl(120, 100%, 40%);">+#define  PCR_DMI_DMICTL_SRLOCK  (1 << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define PCR_DMI_ACPIBA             0x27B4</span><br><span> #define PCR_DMI_ACPIBDID      0x27B8</span><br><span> #define PCR_DMI_PMBASEA               0x27AC</span><br><span>@@ -168,23 +171,38 @@</span><br><span>       outw(tcocnt, tcobase + TCO1_CNT);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static int pch_check_decode_enable(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+       uint32_t dmi_control;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+       /*</span><br><span style="color: hsl(120, 100%, 40%);">+     * This cycle decoding is only allowed to set when</span><br><span style="color: hsl(120, 100%, 40%);">+     * DMICTL.SRLOCK is 0.</span><br><span style="color: hsl(120, 100%, 40%);">+         */</span><br><span style="color: hsl(120, 100%, 40%);">+   dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL);</span><br><span style="color: hsl(120, 100%, 40%);">+    if (dmi_control & PCR_DMI_DMICTL_SRLOCK)</span><br><span style="color: hsl(120, 100%, 40%);">+          return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+    return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void pch_early_iorange_init(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-        uint16_t dec_rng, dec_en = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |</span><br><span style="color: hsl(120, 100%, 40%);">+             LPC_IOE_EC_62_66 | LPC_IOE_LGE_200;</span><br><span> </span><br><span>      /* IO Decode Range */</span><br><span style="color: hsl(0, 100%, 40%);">-   if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) &&</span><br><span style="color: hsl(0, 100%, 40%);">-       IS_ENABLED(CONFIG_UART_DEBUG)) {</span><br><span style="color: hsl(0, 100%, 40%);">-            dec_rng = COMA_RANGE | (COMB_RANGE << 4);</span><br><span style="color: hsl(0, 100%, 40%);">-         dec_en = COMA_LPC_EN | COMB_LPC_EN;</span><br><span style="color: hsl(0, 100%, 40%);">-             pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, dec_rng);</span><br><span style="color: hsl(0, 100%, 40%);">-           pcr_write16(PID_DMI, PCR_DMI_LPCIOD, dec_rng);</span><br><span style="color: hsl(0, 100%, 40%);">-  }</span><br><span style="color: hsl(120, 100%, 40%);">+     if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO))</span><br><span style="color: hsl(120, 100%, 40%);">+           lpc_io_setup_comm_a_b();</span><br><span> </span><br><span>         /* IO Decode Enable */</span><br><span style="color: hsl(0, 100%, 40%);">-  dec_en |= SE_LPC_EN | KBC_LPC_EN | MC1_LPC_EN | GAMEL_LPC_EN;</span><br><span style="color: hsl(0, 100%, 40%);">-   pci_write_config16(PCH_DEV_LPC, LPC_EN, dec_en);</span><br><span style="color: hsl(0, 100%, 40%);">-        pcr_write16(PID_DMI, PCR_DMI_LPCIOE, dec_en);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pch_check_decode_enable() == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+         io_enables = lpc_enable_fixed_io_ranges(io_enables);</span><br><span style="color: hsl(120, 100%, 40%);">+          /*</span><br><span style="color: hsl(120, 100%, 40%);">+             * Set up LPC IO Enables PCR[DMI] + 2774h [15:0] to the same</span><br><span style="color: hsl(120, 100%, 40%);">+           * value program in LPC PCI offset 82h.</span><br><span style="color: hsl(120, 100%, 40%);">+                */</span><br><span style="color: hsl(120, 100%, 40%);">+           pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);</span><br><span style="color: hsl(120, 100%, 40%);">+     }</span><br><span> </span><br><span>        /* Program generic IO Decode Range */</span><br><span>        pch_enable_lpc();</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/29671">change 29671</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/29671"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I9bd894fea62b78b81e5c80b5e88a539ebddac2df </div>
<div style="display:none"> Gerrit-Change-Number: 29671 </div>
<div style="display:none"> Gerrit-PatchSet: 2 </div>
<div style="display:none"> Gerrit-Owner: Duncan Laurie <dlaurie@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: Duncan Laurie <dlaurie@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: Lijian Zhao <lijian.zhao@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-MessageType: merged </div>