<p>Shelley Chen would like Subrata Banik to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/c/coreboot/+/29753">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/dragonegg: Patch for Audio Enabling<br><br>1. Enable Boot Beep support<br>2. Enable Audio over Speaker<br><br>Change-Id: Ia4843185dd79a35476c4f0fc0666ebaf3773db4c<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb<br>M src/mainboard/google/dragonegg/variants/baseboard/gpio.c<br>2 files changed, 40 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/29753/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb</span><br><span>index b494ac9..051cc66 100644</span><br><span>--- a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb</span><br><span>+++ b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb</span><br><span>@@ -12,6 +12,11 @@</span><br><span> device lapic 0 on end</span><br><span> end</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ register "EnableAzalia" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PchHdaDspEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PchHdaAudioLinkSsp0" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PchHdaAudioLinkSsp1" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> # FSP configuration</span><br><span> register "SaGv" = "SaGv_Disabled"</span><br><span> register "SmbusEnable" = "1"</span><br><span>@@ -152,6 +157,15 @@</span><br><span> .speed_mhz = 1,</span><br><span> .early_init = 1,</span><br><span> },</span><br><span style="color: hsl(120, 100%, 40%);">+ .i2c[3] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed = I2C_SPEED_FAST,</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed_config[0] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed = I2C_SPEED_FAST,</span><br><span style="color: hsl(120, 100%, 40%);">+ .scl_lcnt = 176,</span><br><span style="color: hsl(120, 100%, 40%);">+ .scl_hcnt = 95,</span><br><span style="color: hsl(120, 100%, 40%);">+ .sda_hold = 36,</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span> }"</span><br><span> </span><br><span> device domain 0 on</span><br><span>@@ -237,7 +251,24 @@</span><br><span> end</span><br><span> end # I2C #1</span><br><span> device pci 15.2 on end # I2C #2</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 15.3 on end # I2C #3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.3 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/i2c/max98373</span><br><span style="color: hsl(120, 100%, 40%);">+ register "vmon_slot_no" = "4"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "imon_slot_no" = "5"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "uid" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""RIGHT SPEAKER AMP""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "name" = ""MAXR""</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 31 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/i2c/max98373</span><br><span style="color: hsl(120, 100%, 40%);">+ register "vmon_slot_no" = "6"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "imon_slot_no" = "7"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "uid" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""LEFT SPEAKER AMP""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "name" = ""MAXL""</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 32 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # I2C #3</span><br><span> device pci 16.0 on end # Management Engine Interface 1</span><br><span> device pci 16.1 off end # Management Engine Interface 2</span><br><span> device pci 16.2 off end # Management Engine IDE-R</span><br><span>diff --git a/src/mainboard/google/dragonegg/variants/baseboard/gpio.c b/src/mainboard/google/dragonegg/variants/baseboard/gpio.c</span><br><span>index acb3171..fddcc19 100644</span><br><span>--- a/src/mainboard/google/dragonegg/variants/baseboard/gpio.c</span><br><span>+++ b/src/mainboard/google/dragonegg/variants/baseboard/gpio.c</span><br><span>@@ -49,12 +49,20 @@</span><br><span> /* USB_C0_SBU_2_DC */ PAD_CFG_GPO(GPP_E23, 0, DEEP),</span><br><span> /* CNV_RF_RESET_N */ PAD_CFG_NF(GPP_F4, DN_20K, PWROK, NF1),</span><br><span> /* CNV_CLKREQ0 */ PAD_CFG_NF(GPP_F5, DN_20K, PWROK, NF2),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPKR_IRQ_L */ PAD_CFG_GPI_APIC(GPP_F6, NONE, DEEP, LEVEL, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPKR_RST_L */ PAD_CFG_GPO(GPP_F19, 1, DEEP),</span><br><span> /* SD_CD# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_G5, UP_20K, DEEP),</span><br><span> /* SD_WP */ PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C3_SDA */ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C3_SCL */ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),</span><br><span> /* PCH_MEM_STRAP0 */ PAD_CFG_GPI(GPP_H12, DN_20K, PLTRST),</span><br><span> /* PCH_MEM_STRAP1 */ PAD_CFG_GPI(GPP_H13, DN_20K, PLTRST),</span><br><span> /* PCH_MEM_STRAP2 */ PAD_CFG_GPI(GPP_H14, DN_20K, PLTRST),</span><br><span> /* PCH_MEM_STRAP3 */ PAD_CFG_GPI(GPP_H15, DN_20K, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S0_SCLK */ PAD_CFG_GPO(GPP_R0, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S0_SFRM */ PAD_CFG_GPO(GPP_R1, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S0_TXD */ PAD_CFG_GPO(GPP_R2, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S0_RXD */ PAD_CFG_GPI(GPP_R3, NONE, DEEP),</span><br><span> };</span><br><span> /* Early pad configuration in bootblock */</span><br><span> static const struct pad_config early_gpio_table[] = {</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/29753">change 29753</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/29753"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: Ia4843185dd79a35476c4f0fc0666ebaf3773db4c </div>
<div style="display:none"> Gerrit-Change-Number: 29753 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Shelley Chen <shchen@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>