<p>Shelley Chen would like Aamir Bohra to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/c/coreboot/+/29749">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/dragonegg: Add initial mainboard code support<br><br>This patch includes support for both ICL ES0 and ES1 samples.<br><br>Change-Id: I2cc269cb0050bf5b031f48cfe114485c55ab8fa9<br>Signed-off-by: Aamir Bohra <aamir.bohra@intel.com><br>---<br>A src/mainboard/google/dragonegg/Kconfig<br>A src/mainboard/google/dragonegg/Kconfig.name<br>A src/mainboard/google/dragonegg/Makefile.inc<br>A src/mainboard/google/dragonegg/acpi_tables.c<br>A src/mainboard/google/dragonegg/board_info.txt<br>A src/mainboard/google/dragonegg/bootblock.c<br>A src/mainboard/google/dragonegg/chromeos.c<br>A src/mainboard/google/dragonegg/chromeos.fmd<br>A src/mainboard/google/dragonegg/dsdt.asl<br>A src/mainboard/google/dragonegg/ec.c<br>A src/mainboard/google/dragonegg/mainboard.c<br>A src/mainboard/google/dragonegg/ramstage.c<br>A src/mainboard/google/dragonegg/romstage.c<br>A src/mainboard/google/dragonegg/smihandler.c<br>A src/mainboard/google/dragonegg/spd/Hynix_H9HCNNN8KUMLHR_2GB.spd.hex<br>A src/mainboard/google/dragonegg/spd/Hynix_H9HCNNNCPMMLHR_4GB.spd.hex<br>A src/mainboard/google/dragonegg/spd/Makefile.inc<br>A src/mainboard/google/dragonegg/spd/Micron_MT53E2G32D8QD_8GB.spd.hex<br>A src/mainboard/google/dragonegg/spd/Micron_MT53E512M32D2NP_2GB.spd.hex<br>A src/mainboard/google/dragonegg/spd/empty.spd.hex<br>A src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc<br>A src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb<br>A src/mainboard/google/dragonegg/variants/baseboard/gpio.c<br>A src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/ec.h<br>A src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/gpio.h<br>A src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/variants.h<br>A src/mainboard/google/dragonegg/variants/baseboard/memory.c<br>A src/mainboard/google/dragonegg/variants/dragonegg/include/variant/ec.h<br>A src/mainboard/google/dragonegg/variants/dragonegg/include/variant/gpio.h<br>29 files changed, 1,357 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/29749/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/dragonegg/Kconfig b/src/mainboard/google/dragonegg/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..e29ed17</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/dragonegg/Kconfig</span><br><span>@@ -0,0 +1,83 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_GOOGLE_BASEBOARD_DRAGONEGG</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool y</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_ROMSIZE_KB_32768</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_I2C_GENERIC</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_I2C_HID</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_SPI_ACPI</span><br><span style="color: hsl(120, 100%, 40%);">+ select EC_GOOGLE_CHROMEEC</span><br><span style="color: hsl(120, 100%, 40%);">+ select EC_GOOGLE_CHROMEEC_LPC</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_RESUME</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_TABLES</span><br><span style="color: hsl(120, 100%, 40%);">+ select MAINBOARD_HAS_CHROMEOS</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_ICELAKE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_GOOGLE_BASEBOARD_DRAGONEGG</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config CHROMEOS</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default y</span><br><span style="color: hsl(120, 100%, 40%);">+ select GBB_FLAG_FORCE_MANUAL_RECOVERY</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config DEVICETREE</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "variants/baseboard/devicetree.cb"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config DIMM_SPD_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 512</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# Select this option to enable use of cr50 SPI TPM on dragon egg.</span><br><span style="color: hsl(120, 100%, 40%);">+config DRAGONEGG_USE_SPI_TPM</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default y</span><br><span style="color: hsl(120, 100%, 40%);">+ select MAINBOARD_HAS_SPI_TPM_CR50</span><br><span style="color: hsl(120, 100%, 40%);">+ select MAINBOARD_HAS_TPM2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config DRIVER_TPM_SPI_BUS</span><br><span style="color: hsl(120, 100%, 40%);">+ depends on DRAGONEGG_USE_SPI_TPM</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config GBB_HWID</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ depends on CHROMEOS</span><br><span style="color: hsl(120, 100%, 40%);">+ default "DRAGONEGG TEST 1394"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_DIR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "google/dragonegg"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PART_NUMBER</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "Dragonegg"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_VENDOR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "Google"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_FAMILY</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "Google_Dragonegg"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAX_CPUS</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config TPM_TIS_ACPI_INTERRUPT</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 48 # GPE0_DW1_16 (GPP_D16)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config VARIANT_DIR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "dragonegg" if BOARD_GOOGLE_DRAGONEGG</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config UART_FOR_CONSOLE</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config VBOOT</span><br><span style="color: hsl(120, 100%, 40%);">+ select VBOOT_LID_SWITCH</span><br><span style="color: hsl(120, 100%, 40%);">+ select EC_GOOGLE_CHROMEEC_SWITCHES</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAS_RECOVERY_MRC_CACHE</span><br><span style="color: hsl(120, 100%, 40%);">+ select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endif # BOARD_GOOGLE_BASEBOARD_DRAGONEGG</span><br><span>diff --git a/src/mainboard/google/dragonegg/Kconfig.name b/src/mainboard/google/dragonegg/Kconfig.name</span><br><span>new file mode 100644</span><br><span>index 0000000..5c5fe21</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/dragonegg/Kconfig.name</span><br><span>@@ -0,0 +1,5 @@</span><br><span style="color: hsl(120, 100%, 40%);">+comment "Dragon Egg"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_GOOGLE_DRAGONEGG</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "-> Dragon Egg"</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_GOOGLE_BASEBOARD_DRAGONEGG</span><br><span>diff --git a/src/mainboard/google/dragonegg/Makefile.inc b/src/mainboard/google/dragonegg/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..58a4ebb</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/dragonegg/Makefile.inc</span><br><span>@@ -0,0 +1,36 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += bootblock.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-$(CONFIG_CHROMEOS) += chromeos.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-$(CONFIG_CHROMEOS) += chromeos.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-$(CONFIG_CHROMEOS) += chromeos.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_CHROMEOS) += chromeos.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += mainboard.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += ramstage.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+subdirs-y += variants/baseboard</span><br><span style="color: hsl(120, 100%, 40%);">+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+subdirs-y += variants/$(VARIANT_DIR)</span><br><span style="color: hsl(120, 100%, 40%);">+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+subdirs-y += spd</span><br><span>diff --git a/src/mainboard/google/dragonegg/acpi_tables.c b/src/mainboard/google/dragonegg/acpi_tables.c</span><br><span>new file mode 100644</span><br><span>index 0000000..e69de29</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/dragonegg/acpi_tables.c</span><br><span>diff --git a/src/mainboard/google/dragonegg/board_info.txt b/src/mainboard/google/dragonegg/board_info.txt</span><br><span>new file mode 100644</span><br><span>index 0000000..ce11aa6</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/dragonegg/board_info.txt</span><br><span>@@ -0,0 +1,6 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Vendor name: google</span><br><span style="color: hsl(120, 100%, 40%);">+Board name: Dragon Egg</span><br><span style="color: hsl(120, 100%, 40%);">+Category: Proto</span><br><span style="color: hsl(120, 100%, 40%);">+ROM protocol: SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ROM socketed: n</span><br><span style="color: hsl(120, 100%, 40%);">+Flashrom support: y</span><br><span>diff --git a/src/mainboard/google/dragonegg/bootblock.c b/src/mainboard/google/dragonegg/bootblock.c</span><br><span>new file mode 100644</span><br><span>index 0000000..8655947</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/dragonegg/bootblock.c</span><br><span>@@ -0,0 +1,28 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variants.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <bootblock_common.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <variant/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_mainboard_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct pad_config *pads;</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t num;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pads = variant_early_gpio_table(&num);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_configure_pads(pads, num);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/google/dragonegg/chromeos.c b/src/mainboard/google/dragonegg/chromeos.c</span><br><span>new file mode 100644</span><br><span>index 0000000..fa388e5</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/dragonegg/chromeos.c</span><br><span>@@ -0,0 +1,56 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variants.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <rules.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <vendorcode/google/chromeos/chromeos.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <variant/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if ENV_RAMSTAGE</span><br><span style="color: hsl(120, 100%, 40%);">+#include <boot/coreboot_tables.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void fill_lb_gpios(struct lb_gpios *gpios)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct lb_gpio chromeos_gpios[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {-1, ACTIVE_HIGH, 0, "power"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW),</span><br><span style="color: hsl(120, 100%, 40%);">+ "EC in RW"},</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* ENV_RAMSTAGE */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int get_write_protect_state(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Read PCH_WP GPIO. */</span><br><span style="color: hsl(120, 100%, 40%);">+ return gpio_get(GPIO_PCH_WP);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_chromeos_acpi_generate(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct cros_gpio *gpios;</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t num;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ gpios = variant_cros_gpios(&num);</span><br><span style="color: hsl(120, 100%, 40%);">+ chromeos_acpi_gpio_generate(gpios, num);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/google/dragonegg/chromeos.fmd b/src/mainboard/google/dragonegg/chromeos.fmd</span><br><span>new file mode 100644</span><br><span>index 0000000..07a6987</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/dragonegg/chromeos.fmd</span><br><span>@@ -0,0 +1,42 @@</span><br><span style="color: hsl(120, 100%, 40%);">+FLASH@0xfe000000 0x2000000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ SI_ALL@0x0 0x3F0000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ SI_DESC@0x0 0x1000</span><br><span style="color: hsl(120, 100%, 40%);">+ SI_ME@0x1000 0x36F000</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ SI_BIOS@0x1400000 0xC00000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_SECTION_A@0x0 0x2d0000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ VBLOCK_A@0x0 0x10000</span><br><span style="color: hsl(120, 100%, 40%);">+ FW_MAIN_A(CBFS)@0x10000 0x2bffc0</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_FWID_A@0x2cffc0 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_SECTION_B@0x2d0000 0x2d0000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ VBLOCK_B@0x0 0x10000</span><br><span style="color: hsl(120, 100%, 40%);">+ FW_MAIN_B(CBFS)@0x10000 0x2bffc0</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_FWID_B@0x2cffc0 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_MISC@0x5a0000 0x30000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ UNIFIED_MRC_CACHE@0x0 0x20000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ RECOVERY_MRC_CACHE@0x0 0x10000</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_MRC_CACHE@0x10000 0x10000</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_ELOG@0x20000 0x4000</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_SHARED@0x24000 0x4000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ SHARED_DATA@0x0 0x2000</span><br><span style="color: hsl(120, 100%, 40%);">+ VBLOCK_DEV@0x2000 0x2000</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_VPD@0x28000 0x2000</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_NVRAM@0x2a000 0x6000</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_LEGACY(CBFS)@0x5d0000 0x200000</span><br><span style="color: hsl(120, 100%, 40%);">+ WP_RO@0x7d0000 0x430000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ RO_VPD@0x0 0x4000</span><br><span style="color: hsl(120, 100%, 40%);">+ RO_SECTION@0x4000 0x42c000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ FMAP@0x0 0x800</span><br><span style="color: hsl(120, 100%, 40%);">+ RO_FRID@0x800 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+ RO_FRID_PAD@0x840 0x7c0</span><br><span style="color: hsl(120, 100%, 40%);">+ GBB@0x1000 0xef000</span><br><span style="color: hsl(120, 100%, 40%);">+ COREBOOT(CBFS)@0xf0000 0x33c000</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/google/dragonegg/dsdt.asl b/src/mainboard/google/dragonegg/dsdt.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..9763536</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/dragonegg/dsdt.asl</span><br><span>@@ -0,0 +1,61 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include "variant/ec.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include "variant/gpio.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+DefinitionBlock(</span><br><span style="color: hsl(120, 100%, 40%);">+ "dsdt.aml",</span><br><span style="color: hsl(120, 100%, 40%);">+ "DSDT",</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x05, // DSDT revision: ACPI v5.0</span><br><span style="color: hsl(120, 100%, 40%);">+ "COREv4", // OEM id</span><br><span style="color: hsl(120, 100%, 40%);">+ "COREBOOT", // OEM table id</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x20110725 // OEM revision</span><br><span style="color: hsl(120, 100%, 40%);">+)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ // Some generic macros</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/icelake/acpi/platform.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // global NVS and variables</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/icelake/acpi/globalnvs.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // CPU</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/icelake/acpi/cpu.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_SB) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (PCI0)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/icelake/acpi/northbridge.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/icelake/acpi/southbridge.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ #if IS_ENABLED(CONFIG_CHROMEOS)</span><br><span style="color: hsl(120, 100%, 40%);">+ // Chrome OS specific</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <vendorcode/google/chromeos/acpi/chromeos.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // Chipset specific sleep states</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/icelake/acpi/sleepstates.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Chrome OS Embedded Controller */</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_SB.PCI0.LPCB)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ACPI code for EC SuperIO functions */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <ec/google/chromeec/acpi/superio.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ /* ACPI code for EC functions */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <ec/google/chromeec/acpi/ec.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/google/dragonegg/ec.c b/src/mainboard/google/dragonegg/ec.c</span><br><span>new file mode 100644</span><br><span>index 0000000..4fd6807</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/dragonegg/ec.c</span><br><span>@@ -0,0 +1,30 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <ec/google/chromeec/ec.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <variant/ec.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_ec_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct google_chromeec_event_info info = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .log_events = MAINBOARD_EC_LOG_EVENTS,</span><br><span style="color: hsl(120, 100%, 40%);">+ .sci_events = MAINBOARD_EC_SCI_EVENTS,</span><br><span style="color: hsl(120, 100%, 40%);">+ .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,</span><br><span style="color: hsl(120, 100%, 40%);">+ .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ google_chromeec_events_init(&info, acpi_is_wakeup_s3());</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/google/dragonegg/mainboard.c b/src/mainboard/google/dragonegg/mainboard.c</span><br><span>new file mode 100644</span><br><span>index 0000000..3e8fd9f</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/dragonegg/mainboard.c</span><br><span>@@ -0,0 +1,38 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variants.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <ec/ec.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <vendorcode/google/chromeos/chromeos.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <variant/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void mainboard_init(void *chip_info)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ mainboard_ec_init();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void mainboard_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ dev->ops->write_acpi_tables = NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct chip_operations mainboard_ops = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .init = mainboard_init,</span><br><span style="color: hsl(120, 100%, 40%);">+ .enable_dev = mainboard_enable,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/mainboard/google/dragonegg/ramstage.c b/src/mainboard/google/dragonegg/ramstage.c</span><br><span>new file mode 100644</span><br><span>index 0000000..1719a07</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/dragonegg/ramstage.c</span><br><span>@@ -0,0 +1,27 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variants.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/ramstage.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <variant/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_silicon_init_params(FSP_S_CONFIG *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t num;</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct pad_config *gpio_table;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_table = variant_gpio_table(&num);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_configure_pads(gpio_table, num);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/google/dragonegg/romstage.c b/src/mainboard/google/dragonegg/romstage.c</span><br><span>new file mode 100644</span><br><span>index 0000000..633f69e</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/dragonegg/romstage.c</span><br><span>@@ -0,0 +1,25 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <assert.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variants.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbfs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/romstage.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_memory_init_params(FSPM_UPD *mupd)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/google/dragonegg/smihandler.c b/src/mainboard/google/dragonegg/smihandler.c</span><br><span>new file mode 100644</span><br><span>index 0000000..f1db9b7</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/dragonegg/smihandler.c</span><br><span>@@ -0,0 +1,40 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/smm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <ec/google/chromeec/smm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/smm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <variant/ec.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_smi_espi_handler(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ chromeec_smi_process_events();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_smi_sleep(u8 slp_typ)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,</span><br><span style="color: hsl(120, 100%, 40%);">+ MAINBOARD_EC_S5_WAKE_EVENTS);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int mainboard_smi_apmc(u8 apmc)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,</span><br><span style="color: hsl(120, 100%, 40%);">+ MAINBOARD_EC_SMI_EVENTS);</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>diff --git a/src/mainboard/google/dragonegg/spd/Hynix_H9HCNNN8KUMLHR_2GB.spd.hex b/src/mainboard/google/dragonegg/spd/Hynix_H9HCNNN8KUMLHR_2GB.spd.hex</span><br><span>new file mode 100644</span><br><span>index 0000000..d9014dc</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/dragonegg/spd/Hynix_H9HCNNN8KUMLHR_2GB.spd.hex</span><br><span>@@ -0,0 +1,32 @@</span><br><span style="color: hsl(120, 100%, 40%);">+23 11 11 0E 15 21 91 08 00 40 00 00 02 22 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 05 32 92 55 00 00 8C 00 90 A8 90 C0 08 60</span><br><span style="color: hsl(120, 100%, 40%);">+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 9E 00 A7 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span>diff --git a/src/mainboard/google/dragonegg/spd/Hynix_H9HCNNNCPMMLHR_4GB.spd.hex b/src/mainboard/google/dragonegg/spd/Hynix_H9HCNNNCPMMLHR_4GB.spd.hex</span><br><span>new file mode 100644</span><br><span>index 0000000..2f2b18a</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/dragonegg/spd/Hynix_H9HCNNNCPMMLHR_4GB.spd.hex</span><br><span>@@ -0,0 +1,32 @@</span><br><span style="color: hsl(120, 100%, 40%);">+23 11 11 0E 15 21 B1 08 00 40 00 00 0A 22 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+48 00 05 32 92 55 00 00 8C 00 90 A8 90 C0 08 60</span><br><span style="color: hsl(120, 100%, 40%);">+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 9E 00 A7 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span>diff --git a/src/mainboard/google/dragonegg/spd/Makefile.inc b/src/mainboard/google/dragonegg/spd/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..7aa9505</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/dragonegg/spd/Makefile.inc</span><br><span>@@ -0,0 +1,39 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_BIN = $(obj)/spd.bin</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES = Hynix_H9HCNNN8KUMLHR_2GB # 0b000</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += Hynix_H9HCNNNCPMMLHR_4GB # 0b001</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += Micron_MT53E512M32D2NP_2GB # 0b010</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += Micron_MT53E2G32D8QD_8GB # 0b011</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ifeq ($(SPD_SOURCES),)</span><br><span style="color: hsl(120, 100%, 40%);">+ SPD_DEPS := $(error SPD_SOURCES is not set. Variant must provide this)</span><br><span style="color: hsl(120, 100%, 40%);">+else</span><br><span style="color: hsl(120, 100%, 40%);">+ SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)</span><br><span style="color: hsl(120, 100%, 40%);">+endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# Include spd ROM data</span><br><span style="color: hsl(120, 100%, 40%);">+$(SPD_BIN): $(SPD_DEPS)</span><br><span style="color: hsl(120, 100%, 40%);">+ for f in $+; \</span><br><span style="color: hsl(120, 100%, 40%);">+ do for c in $$(cat $$f | grep -v ^#); \</span><br><span style="color: hsl(120, 100%, 40%);">+ do printf $$(printf '\%o' 0x$$c); \</span><br><span style="color: hsl(120, 100%, 40%);">+ done; \</span><br><span style="color: hsl(120, 100%, 40%);">+ done > $@</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+cbfs-files-y += spd.bin</span><br><span style="color: hsl(120, 100%, 40%);">+spd.bin-file := $(SPD_BIN)</span><br><span style="color: hsl(120, 100%, 40%);">+spd.bin-type := spd</span><br><span>diff --git a/src/mainboard/google/dragonegg/spd/Micron_MT53E2G32D8QD_8GB.spd.hex b/src/mainboard/google/dragonegg/spd/Micron_MT53E2G32D8QD_8GB.spd.hex</span><br><span>new file mode 100644</span><br><span>index 0000000..856c05e</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/dragonegg/spd/Micron_MT53E2G32D8QD_8GB.spd.hex</span><br><span>@@ -0,0 +1,32 @@</span><br><span style="color: hsl(120, 100%, 40%);">+23 11 11 0E 15 29 F0 08 00 40 00 00 09 22 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 05 0F 12 29 05 00 8A 00 90 A8 90 C0 08 60</span><br><span style="color: hsl(120, 100%, 40%);">+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 92 00 A7 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20</span><br><span style="color: hsl(120, 100%, 40%);">+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span>diff --git a/src/mainboard/google/dragonegg/spd/Micron_MT53E512M32D2NP_2GB.spd.hex b/src/mainboard/google/dragonegg/spd/Micron_MT53E512M32D2NP_2GB.spd.hex</span><br><span>new file mode 100644</span><br><span>index 0000000..71e5456</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/dragonegg/spd/Micron_MT53E512M32D2NP_2GB.spd.hex</span><br><span>@@ -0,0 +1,32 @@</span><br><span style="color: hsl(120, 100%, 40%);">+23 11 11 0E 15 21 90 08 00 40 00 00 02 22 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60</span><br><span style="color: hsl(120, 100%, 40%);">+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 E1 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20</span><br><span style="color: hsl(120, 100%, 40%);">+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span>diff --git a/src/mainboard/google/dragonegg/spd/empty.spd.hex b/src/mainboard/google/dragonegg/spd/empty.spd.hex</span><br><span>new file mode 100644</span><br><span>index 0000000..67b46cd</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/dragonegg/spd/empty.spd.hex</span><br><span>@@ -0,0 +1,32 @@</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span>diff --git a/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc b/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..22736b9</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc</span><br><span>@@ -0,0 +1,20 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += memory.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += gpio.c</span><br><span>diff --git a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..da7ee5a</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb</span><br><span>@@ -0,0 +1,281 @@</span><br><span style="color: hsl(120, 100%, 40%);">+chip soc/intel/icelake</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # GPE configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ # Note that GPE events called out in ASL code rely on this</span><br><span style="color: hsl(120, 100%, 40%);">+ # route. i.e. If this route changes then the affected GPE</span><br><span style="color: hsl(120, 100%, 40%);">+ # offset bits also need to be changed.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw0" = "PMC_GPP_B"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw1" = "PMC_GPP_D"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw2" = "PMC_GPP_C"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # FSP configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SaGv" = "SaGv_Disabled"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SmbusEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ScsEmmcHs400Enabled" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[1]" = "USB2_PORT_LONG(OC2)" # Type-C Port 2</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[2]" = "USB2_PORT_LONG(OC2)" # Type-C Port 3</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # Type-A</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable Pch iSCLK</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pch_isclk" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen1_dec" = "0x00fc0801"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen2_dec" = "0x000c0201"</span><br><span style="color: hsl(120, 100%, 40%);">+ # EC memory map range is 0x900-0x9ff</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen3_dec" = "0x00fc0901"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PrmrrSize" = "0x10000000"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[0]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[1]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[2]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[3]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[4]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[5]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[6]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[7]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[8]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[9]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[10]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[11]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[12]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[13]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[14]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[15]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[0]" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[1]" = "7"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[2]" = "8"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[3]" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[4]" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[5]" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[6]" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[7]" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[8]" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[9]" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[10]" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[11]" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[12]" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[13]" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[14]" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[15]" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[0]" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[1]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[2]" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[3]" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[4]" = "4"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[5]" = "5"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[6]" = "6"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[7]" = "7"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[8]" = "8"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[9]" = "9"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[10]" = "10"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[11]" = "11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[12]" = "12"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[13]" = "13"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[14]" = "14"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[15]" = "15"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SerialIoI2cMode" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C0] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C1] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C2] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C3] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C4] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C5] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SerialIoGSpiMode" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexGSPI0] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexGSPI1] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexGSPI2] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SerialIoGSpiCsMode" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexGSPI0] = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexGSPI1] = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexGSPI2] = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SerialIoGSpiCsState" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexGSPI0] = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexGSPI1] = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexGSPI2] = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SerialIoUartMode" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexUART0] = PchSerialIoSkipInit,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexUART1] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexUART2] = PchSerialIoSkipInit,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable "Intel Speed Shift Technology"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "speed_shift_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # GPIO for SD card detect</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sdcard_cd_gpio" = "GPP_G5"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable S0ix</span><br><span style="color: hsl(120, 100%, 40%);">+ register "s0ix_enable" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Intel Common SoC Config</span><br><span style="color: hsl(120, 100%, 40%);">+ #+-------------------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Field | Value |</span><br><span style="color: hsl(120, 100%, 40%);">+ #+-------------------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| GSPI0 | cr50 TPM. Early init is |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| | required to set up a BAR |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| | for TPM communication |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| | before memory is up |</span><br><span style="color: hsl(120, 100%, 40%);">+ #+-------------------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "common_soc_config" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gspi[0] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed_mhz = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .early_init = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end # Host Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 on end # Integrated Graphics Device</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 04.0 off end # SA Thermal device</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.0 off end # Thermal Subsystem</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.5 off end # UFS SCS</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.6 off end # GSPI #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""Root Hub""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_HUB"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 0.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""USB2 Type-C Right""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 2.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""USB3 Type-C Rear Left""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 2.1 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""USB3 Type-C Front Left""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 2.2 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""USB3 Type-A Right""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_USB3_A"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 2.3 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""USB2 Bluetooth""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_INTERNAL"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 2.4 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""USB2 Camera""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_INTERNAL"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 2.5 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""USB3 Type-C Right""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 3.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""USB3 Type-C Rear Left""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_USB3_A"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 3.1 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""USB3 Type-C Front Right""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_USB3_A"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 3.2 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""USB3 Type-A Right""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_USB3_A"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 3.3 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # USB xHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.2 off end # PMC SRAM</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.1 off end # USB xDCI (OTG)</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/intel/wifi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "wake" = "GPE0_PME_B0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.3 on end # CNVi wifi</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.5 on end # SDCard</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.0 on end # I2C #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.1 on end # I2C #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.2 on end # I2C #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.3 on end # I2C #3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 on end # Management Engine Interface 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.1 off end # Management Engine Interface 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.2 off end # Management Engine IDE-R</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.3 off end # Management Engine KT Redirection</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.4 off end # Management Engine Interface 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.5 off end # Management Engine Interface 4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.0 off end # SATA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.0 on end # I2C #4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.1 off end # I2C #5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.2 on end # UART #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.0 on end # eMMC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/intel/wifi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "wake" = "GPE0_DW0_06"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # PCI Express Port 1 x4 SLOT1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.4 off end # PCI Express Port 5 x1 SLOT2/LAN</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.5 off end # PCI Express Port 6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.6 off end # PCI Express Port 7</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.7 off end # PCI Express Port 8</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 on end # PCI Express Port 9</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.1 off end # PCI Express Port 10</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.2 off end # PCI Express Port 11</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.3 off end # PCI Express Port 12</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.4 off end # PCI Express Port 13</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.5 off end # PCI Express Port 14</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.6 off end # PCI Express Port 15</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.7 off end # PCI Express Port 16</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 on end # UART #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.1 off end # UART #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.2 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/spi/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "hid" = "ACPI_DT_NAMESPACE_HID"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "compat_string" = ""google,cr50""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"</span><br><span style="color: hsl(120, 100%, 40%);">+ device spi 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # GSPI #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.3 off end # GSPI #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on end # LPC Interface</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.1 on end # P2SB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.2 on end # Power Management Controller</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 off end # Intel HDA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.4 on end # SMBus</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.5 on end # PCH SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.6 off end # GbE</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/google/dragonegg/variants/baseboard/gpio.c b/src/mainboard/google/dragonegg/variants/baseboard/gpio.c</span><br><span>new file mode 100644</span><br><span>index 0000000..6e0928f</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/dragonegg/variants/baseboard/gpio.c</span><br><span>@@ -0,0 +1,88 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variants.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <commonlib/helpers.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Pad configuration in ramstage*/</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_config gpio_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S2_SCLK */ PAD_CFG_GPI(GPP_A7, NONE, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S2_RXD */ PAD_CFG_GPI(GPP_A10, NONE, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ONBOARD_X4_PCIE_SLOT1_PWREN_N */ PAD_CFG_GPO(GPP_A14, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB_OC_ODL */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* WLAN_PCIE_WAKE_L */ PAD_CFG_GPI_SCI(GPP_B6, NONE, DEEP, EDGE_SINGLE,</span><br><span style="color: hsl(120, 100%, 40%);">+ INVERT),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH_WP_OD */ PAD_CFG_GPI(GPP_B7, UP_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH_SPI_FPMCU_F7_CS_L */ PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PEN_INT_ODL */ PAD_CFG_GPI(GPP_C2, NONE, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPP_C5_STRAP */ PAD_CFG_GPO(GPP_C5, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TCH_INT_ODL */ PAD_CFG_GPI(GPP_C10, NONE, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TCH_RST_ODL */ PAD_CFG_GPO(GPP_C11, 0, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+/* M2_SHUTDOWN+L */ PAD_CFG_GPO(GPP_C12, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+/* M2_RESET_L */ PAD_CFG_GPO(GPP_C13, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+/* M2_INT_L */ PAD_CFG_GPI(GPP_C14, NONE, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+/* HP_INT_L */ PAD_CFG_GPI(GPP_C15, NONE, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH_DEV_INT_ODL */ PAD_CFG_GPI(GPP_C22, NONE, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH_DEV_RESET_L */ PAD_CFG_GPO(GPP_C23, 0, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCI_NVME_CLKREQ_ODL */ PAD_CFG_NF(GPP_D7, UP_20K, PWROK, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_D16, UP_20K, PLTRST, LEVEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ INVERT),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPP_E6_STRAP */ PAD_CFG_GPO(GPP_E6, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB_C0_SBU_1_DC */ PAD_CFG_GPO(GPP_E22, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB_C0_SBU_2_DC */ PAD_CFG_GPO(GPP_E23, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CNV_RF_RESET_N */ PAD_CFG_NF(GPP_F4, DN_20K, PWROK, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CNV_CLKREQ0 */ PAD_CFG_NF(GPP_F5, DN_20K, PWROK, NF2),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CD# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_G5, UP_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_WP */ PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH_MEM_STRAP0 */ PAD_CFG_GPI(GPP_H12, DN_20K, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH_MEM_STRAP1 */ PAD_CFG_GPI(GPP_H13, DN_20K, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH_MEM_STRAP2 */ PAD_CFG_GPI(GPP_H14, DN_20K, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH_MEM_STRAP3 */ PAD_CFG_GPI(GPP_H15, DN_20K, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+/* Early pad configuration in bootblock */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_config early_gpio_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH_WP_OD */ PAD_CFG_GPI(GPP_B7, UP_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_D16, UP_20K, PLTRST, LEVEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ INVERT),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config *__attribute__((weak)) variant_gpio_table(size_t *num)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *num = ARRAY_SIZE(gpio_table);</span><br><span style="color: hsl(120, 100%, 40%);">+ return gpio_table;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config *__attribute__((weak))</span><br><span style="color: hsl(120, 100%, 40%);">+ variant_early_gpio_table(size_t *num)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *num = ARRAY_SIZE(early_gpio_table);</span><br><span style="color: hsl(120, 100%, 40%);">+ return early_gpio_table;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct cros_gpio cros_gpios[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),</span><br><span style="color: hsl(120, 100%, 40%);">+ CROS_GPIO_WP_AH(39, CROS_GPIO_DEVICE_NAME),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct cros_gpio *__attribute__((weak)) variant_cros_gpios(size_t *num)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *num = ARRAY_SIZE(cros_gpios);</span><br><span style="color: hsl(120, 100%, 40%);">+ return cros_gpios;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/ec.h</span><br><span>new file mode 100644</span><br><span>index 0000000..7a2ec19</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/ec.h</span><br><span>@@ -0,0 +1,83 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __BASEBOARD_EC_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#define __BASEBOARD_EC_H__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <ec/ec.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <ec/google/chromeec/ec_commands.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <variant/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAINBOARD_EC_SCI_EVENTS \</span><br><span style="color: hsl(120, 100%, 40%);">+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAINBOARD_EC_SMI_EVENTS \</span><br><span style="color: hsl(120, 100%, 40%);">+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* EC can wake from S5 with lid or power button */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAINBOARD_EC_S5_WAKE_EVENTS \</span><br><span style="color: hsl(120, 100%, 40%);">+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * EC can wake from S3 with lid or power button or key press or</span><br><span style="color: hsl(120, 100%, 40%);">+ * mode change event.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAINBOARD_EC_S3_WAKE_EVENTS \</span><br><span style="color: hsl(120, 100%, 40%);">+ (MAINBOARD_EC_S5_WAKE_EVENTS |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Log EC wake events plus EC shutdown events */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAINBOARD_EC_LOG_EVENTS \</span><br><span style="color: hsl(120, 100%, 40%);">+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * ACPI related definitions for ASL code.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Enable EC backed ALS device in ACPI */</span><br><span style="color: hsl(120, 100%, 40%);">+#define EC_ENABLE_ALS_DEVICE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Enable EC backed PD MCU device in ACPI */</span><br><span style="color: hsl(120, 100%, 40%);">+#define EC_ENABLE_PD_MCU_DEVICE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Enable LID switch and provide wake pin for EC */</span><br><span style="color: hsl(120, 100%, 40%);">+#define EC_ENABLE_LID_SWITCH</span><br><span style="color: hsl(120, 100%, 40%);">+#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define EC_ENABLE_MKBP_DEVICE /* Enable cros_ec_keyb device */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* __BASEBOARD_EC_H__ */</span><br><span>diff --git a/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/gpio.h</span><br><span>new file mode 100644</span><br><span>index 0000000..99bbb71</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/gpio.h</span><br><span>@@ -0,0 +1,40 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __BASEBOARD_GPIO_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#define __BASEBOARD_GPIO_H__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpe.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* EC in RW */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_EC_IN_RW GPP_B8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* BIOS Flash Write Protect */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_PCH_WP GPP_B7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* eSPI virtual wire reporting */</span><br><span style="color: hsl(120, 100%, 40%);">+#define EC_SCI_GPI GPE0_ESPI</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE_EC_WAKE GPE0_LAN_WAK</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Memory configuration board straps */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_MEM_CONFIG_0 GPP_H12</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_MEM_CONFIG_1 GPP_H13</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_MEM_CONFIG_2 GPP_H14</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_MEM_CONFIG_3 GPP_H15</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* BASEBOARD_GPIO_H */</span><br><span>diff --git a/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/variants.h</span><br><span>new file mode 100644</span><br><span>index 0000000..37a7c05</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/variants.h</span><br><span>@@ -0,0 +1,43 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __BASEBOARD_VARIANTS_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#define __BASEBOARD_VARIANTS_H__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <vendorcode/google/chromeos/chromeos.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * The next set of functions return the gpio table and fill in the number of</span><br><span style="color: hsl(120, 100%, 40%);">+ * entries for each table.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config *variant_gpio_table(size_t *num);</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config *variant_early_gpio_table(size_t *num);</span><br><span style="color: hsl(120, 100%, 40%);">+const struct cros_gpio *variant_cros_gpios(size_t *num);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct lpddr4_config {</span><br><span style="color: hsl(120, 100%, 40%);">+ const void *dq_map;</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t dq_map_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ const void *dqs_map;</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t dqs_map_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ const void *rcomp_resistor;</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t rcomp_resistor_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ const void *rcomp_target;</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t rcomp_target_size;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+void variant_memory_params(struct lpddr4_config *mem_config);</span><br><span style="color: hsl(120, 100%, 40%);">+int variant_memory_sku(void);</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /*__BASEBOARD_VARIANTS_H__ */</span><br><span>diff --git a/src/mainboard/google/dragonegg/variants/baseboard/memory.c b/src/mainboard/google/dragonegg/variants/baseboard/memory.c</span><br><span>new file mode 100644</span><br><span>index 0000000..51dd610</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/dragonegg/variants/baseboard/memory.c</span><br><span>@@ -0,0 +1,84 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/cpu.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variants.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/mp_init.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <variant/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* DQ byte map */</span><br><span style="color: hsl(120, 100%, 40%);">+static const u8 dq_map[][12] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* DQS CPU<>DRAM map */</span><br><span style="color: hsl(120, 100%, 40%);">+static const u8 dqs_map[][8] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0, 1, 2, 3, 4, 5, 6, 7 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0, 1, 2, 3, 5, 4, 7, 6 },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Rcomp resistor */</span><br><span style="color: hsl(120, 100%, 40%);">+static const u16 rcomp_resistor[] = { 100, 100, 100 };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * get processor id using cpuid eax=1</span><br><span style="color: hsl(120, 100%, 40%);">+ * return value will be in EAX register</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+static uint32_t get_cpuid(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct cpuid_result cpuidr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ cpuidr = cpuid(1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return cpuidr.eax;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void __weak variant_memory_params(struct lpddr4_config *mem_config)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Rcomp target */</span><br><span style="color: hsl(120, 100%, 40%);">+ static const u16 rcomp_target_es0[] = { 80, 40, 40, 40, 30 };</span><br><span style="color: hsl(120, 100%, 40%);">+ static const u16 rcomp_target_es1[] = { 60, 20, 20, 20, 20 };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_config->dq_map = dq_map;</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_config->dq_map_size = sizeof(dq_map);</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_config->dqs_map = dqs_map;</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_config->dqs_map_size = sizeof(dqs_map);</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_config->rcomp_resistor = rcomp_resistor;</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_config->rcomp_resistor_size = sizeof(rcomp_resistor);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (get_cpuid() == CPUID_ICELAKE_A0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_config->rcomp_target = rcomp_target_es0;</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_config->rcomp_target_size = sizeof(rcomp_target_es0);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ else {</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_config->rcomp_target = rcomp_target_es1;</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_config->rcomp_target_size = sizeof(rcomp_target_es1);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int __weak variant_memory_sku(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_t spd_gpios[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_MEM_CONFIG_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_MEM_CONFIG_1,</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_MEM_CONFIG_2,</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_MEM_CONFIG_3,</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/ec.h b/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/ec.h</span><br><span>new file mode 100644</span><br><span>index 0000000..af41bf4</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/ec.h</span><br><span>@@ -0,0 +1,21 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __MAINBOARD_EC_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#define __MAINBOARD_EC_H__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/ec.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* __MAINBOARD_EC_H__ */</span><br><span>diff --git a/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/gpio.h b/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/gpio.h</span><br><span>new file mode 100644</span><br><span>index 0000000..ea1c708</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/gpio.h</span><br><span>@@ -0,0 +1,21 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __MAINBOARD_GPIO_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#define __MAINBOARD_GPIO_H__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* __MAINBOARD_GPIO_H__ */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/29749">change 29749</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/29749"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I2cc269cb0050bf5b031f48cfe114485c55ab8fa9 </div>
<div style="display:none"> Gerrit-Change-Number: 29749 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Shelley Chen <shchen@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Aamir Bohra <aamir.bohra@intel.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>