<p>Frans Hendriks has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29662">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support<br><br>No working C_ENVIRONMENT_BOOTBLOCK support is available.<br>Enable support and add required files for the Braswell Bootblock in C.<br><br>BUG=NA<br>TEST=Portwell PQ7-M107<br><br>Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c<br>Signed-off-by: Frans Hendriks <fhendriks@eltan.com><br>---<br>M src/drivers/intel/fsp1_1/Makefile.inc<br>A src/drivers/intel/fsp1_1/cache_as_ram_cbootblock.S<br>M src/soc/intel/braswell/Kconfig<br>M src/soc/intel/braswell/Makefile.inc<br>A src/soc/intel/braswell/bootblock/bootblock_c.c<br>A src/soc/intel/braswell/include/soc/bootblock.h<br>M src/soc/intel/braswell/romstage/Makefile.inc<br>A src/soc/intel/braswell/romstage/car_stage.S<br>8 files changed, 329 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/29662/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc</span><br><span>index 953d1e4..3b3387e 100644</span><br><span>--- a/src/drivers/intel/fsp1_1/Makefile.inc</span><br><span>+++ b/src/drivers/intel/fsp1_1/Makefile.inc</span><br><span>@@ -3,6 +3,7 @@</span><br><span> #</span><br><span> # Copyright (C) 2014 Sage Electronic Engineering, LLC.</span><br><span> # Copyright (C) 2015 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+# Copyright (C) 2018 Eltan B.V.</span><br><span> #</span><br><span> # This program is free software; you can redistribute it and/or modify</span><br><span> # it under the terms of the GNU General Public License as published by</span><br><span>@@ -22,6 +23,7 @@</span><br><span> </span><br><span> bootblock-y += bootblock.c</span><br><span> bootblock-y += fsp_util.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK)+= cache_as_ram_cbootblock.S</span><br><span> </span><br><span> romstage-y += car.c</span><br><span> romstage-y += fsp_util.c</span><br><span>diff --git a/src/drivers/intel/fsp1_1/cache_as_ram_cbootblock.S b/src/drivers/intel/fsp1_1/cache_as_ram_cbootblock.S</span><br><span>new file mode 100644</span><br><span>index 0000000..70f36a4</span><br><span>--- /dev/null</span><br><span>+++ b/src/drivers/intel/fsp1_1/cache_as_ram_cbootblock.S</span><br><span>@@ -0,0 +1,215 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2008 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Eltan B.V.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_def.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/mtrr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/cache.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/cr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/post_code.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <../../../../../arch/x86/walkcbfs.S></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define LHLT_DELAY 0x50000 /* I/O delay between post codes */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+.global bootblock_pre_c_entry</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock_pre_c_entry:</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+.global cache_as_ram</span><br><span style="color: hsl(120, 100%, 40%);">+cache_as_ram:</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x20)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_SKIP_FSP_CAR)</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * SOC specific setup</span><br><span style="color: hsl(120, 100%, 40%);">+ * NOTE: This has to preserve the registers</span><br><span style="color: hsl(120, 100%, 40%);">+ * mm0, mm1 and edi.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/car_setup.S></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x28)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Find the FSP binary in cbfs.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Make a fake stack that has the return value back to this code.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ lea fake_fsp_stack, %esp</span><br><span style="color: hsl(120, 100%, 40%);">+ jmp find_fsp</span><br><span style="color: hsl(120, 100%, 40%);">+find_fsp_ret:</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Save the FSP location */</span><br><span style="color: hsl(120, 100%, 40%);">+ mov %eax, %ebp</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Only when a valid FSP binary is found at CONFIG_FSP_LOC is</span><br><span style="color: hsl(120, 100%, 40%);">+ * the returned FSP_INFO_HEADER structure address above the base</span><br><span style="color: hsl(120, 100%, 40%);">+ * address of FSP binary specified by the CONFIG_FSP_LOC value.</span><br><span style="color: hsl(120, 100%, 40%);">+ * All of the error values are in the 0x8xxxxxxx range which are</span><br><span style="color: hsl(120, 100%, 40%);">+ * below the CONFIG_FSP_LOC value.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ cmp $CONFIG_FSP_LOC, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ jbe halt1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(POST_FSP_TEMP_RAM_INIT)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Calculate entry into FSP */</span><br><span style="color: hsl(120, 100%, 40%);">+ mov 0x30(%ebp), %eax /* Load TempRamInitEntry */</span><br><span style="color: hsl(120, 100%, 40%);">+ add 0x1c(%ebp), %eax /* add in the offset for FSP */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Pass early init variables on a fake stack (no memory yet)</span><br><span style="color: hsl(120, 100%, 40%);">+ * as well as the return location</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ lea CAR_init_stack, %esp</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * BIST value is zero</span><br><span style="color: hsl(120, 100%, 40%);">+ * eax: TempRamInitApi address</span><br><span style="color: hsl(120, 100%, 40%);">+ * ebp: FSP_INFO_HEADER address</span><br><span style="color: hsl(120, 100%, 40%);">+ * edi: BIST value</span><br><span style="color: hsl(120, 100%, 40%);">+ * esi: Not used</span><br><span style="color: hsl(120, 100%, 40%);">+ * mm0: low 32-bits of TSC value</span><br><span style="color: hsl(120, 100%, 40%);">+ * mm1: high 32-bits of TSC value</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* call FSP binary to setup temporary stack */</span><br><span style="color: hsl(120, 100%, 40%);">+ jmp *%eax</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+CAR_init_done:</span><br><span style="color: hsl(120, 100%, 40%);">+ addl $4, %esp</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * ebp: FSP_INFO_HEADER address</span><br><span style="color: hsl(120, 100%, 40%);">+ * ecx: Temp RAM base</span><br><span style="color: hsl(120, 100%, 40%);">+ * edx: Temp RAM top</span><br><span style="color: hsl(120, 100%, 40%);">+ * edi: BIST value</span><br><span style="color: hsl(120, 100%, 40%);">+ * mm0: low 32-bits of TSC value</span><br><span style="color: hsl(120, 100%, 40%);">+ * mm1: high 32-bits of TSC value</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ cmp $0, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ jne halt2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Setup bootloader stack */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %edx, %esp</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * ebp: FSP_INFO_HEADER address</span><br><span style="color: hsl(120, 100%, 40%);">+ * ecx: Temp RAM base</span><br><span style="color: hsl(120, 100%, 40%);">+ * edx: Temp RAM top</span><br><span style="color: hsl(120, 100%, 40%);">+ * edi: BIST value</span><br><span style="color: hsl(120, 100%, 40%);">+ * esp: Top of stack in temp RAM</span><br><span style="color: hsl(120, 100%, 40%);">+ * mm0: low 32-bits of TSC value</span><br><span style="color: hsl(120, 100%, 40%);">+ * mm1: high 32-bits of TSC value</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Create cache_as_ram_params on stack */</span><br><span style="color: hsl(120, 100%, 40%);">+ pushl %edx /* bootloader CAR end */</span><br><span style="color: hsl(120, 100%, 40%);">+ pushl %ecx /* bootloader CAR begin */</span><br><span style="color: hsl(120, 100%, 40%);">+ pushl %ebp /* FSP_INFO_HEADER */</span><br><span style="color: hsl(120, 100%, 40%);">+ pushl %edi /* bist */</span><br><span style="color: hsl(120, 100%, 40%);">+ movd %mm1, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ pushl %eax /* tsc[63:32] */</span><br><span style="color: hsl(120, 100%, 40%);">+ movd %mm0, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ pushl %eax /* tsc[31:0] */</span><br><span style="color: hsl(120, 100%, 40%);">+ pushl %esp /* pointer to cache_as_ram_params */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Save FSP_INFO_HEADER location in ebx */</span><br><span style="color: hsl(120, 100%, 40%);">+ mov %ebp, %ebx</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* coreboot assumes stack/heap region will be zero */</span><br><span style="color: hsl(120, 100%, 40%);">+ cld</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %ecx, %edi</span><br><span style="color: hsl(120, 100%, 40%);">+ neg %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Only clear up to current stack value. */</span><br><span style="color: hsl(120, 100%, 40%);">+ add %esp, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ shrl $2, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ xorl %eax, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ rep stosl</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Restore the timestamp from bootblock_crt0.S (ebp:mm1) */</span><br><span style="color: hsl(120, 100%, 40%);">+ push %ebp</span><br><span style="color: hsl(120, 100%, 40%);">+ movd %mm1, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ push %eax</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* We can call into C functions now */</span><br><span style="color: hsl(120, 100%, 40%);">+ call bootblock_c_entry</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Never reached */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+halt1:</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Failures for postcode 0xBA - failed in fsp_fih_early_find()</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Values are:</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x01 - FV signature, "_FVH" not present</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x02 - FFS GUID not present</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x03 - FSP INFO Header not found</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP</span><br><span style="color: hsl(120, 100%, 40%);">+ rebased to a different location, or does it need to be?</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x05 - FSP INFO Header signature "FSPH" not found</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x06 - FSP Image ID is not the expected ID.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ movb $0xBA, %ah</span><br><span style="color: hsl(120, 100%, 40%);">+ jmp .Lhlt</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+halt2:</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Failures for postcode 0xBB - failed in the FSP:</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x00 - FSP_SUCCESS: Temp RAM was initialized successfully.</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid.</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met.</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region.</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ movb $0xBB, %ah</span><br><span style="color: hsl(120, 100%, 40%);">+ jmp .Lhlt</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+.Lhlt:</span><br><span style="color: hsl(120, 100%, 40%);">+ xchg %al, %ah</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_POST_IO)</span><br><span style="color: hsl(120, 100%, 40%);">+ outb %al, $CONFIG_POST_IO_PORT</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(POST_DEAD_CODE)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $LHLT_DELAY, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+.Lhlt_Delay:</span><br><span style="color: hsl(120, 100%, 40%);">+ outb %al, $0xED</span><br><span style="color: hsl(120, 100%, 40%);">+ loop .Lhlt_Delay</span><br><span style="color: hsl(120, 100%, 40%);">+ jmp .Lhlt</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * esp is set to this location so that the call into and return from the FSP</span><br><span style="color: hsl(120, 100%, 40%);">+ * in find_fsp will work.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ .align 4</span><br><span style="color: hsl(120, 100%, 40%);">+fake_fsp_stack:</span><br><span style="color: hsl(120, 100%, 40%);">+ .long find_fsp_ret</span><br><span style="color: hsl(120, 100%, 40%);">+ .long CONFIG_FSP_LOC /* FSP base address */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+CAR_init_params:</span><br><span style="color: hsl(120, 100%, 40%);">+ .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */</span><br><span style="color: hsl(120, 100%, 40%);">+ .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */</span><br><span style="color: hsl(120, 100%, 40%);">+ .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */</span><br><span style="color: hsl(120, 100%, 40%);">+ .long CONFIG_ROM_SIZE /* Total FW Length */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+CAR_init_stack:</span><br><span style="color: hsl(120, 100%, 40%);">+ .long CAR_init_done</span><br><span style="color: hsl(120, 100%, 40%);">+ .long CAR_init_params</span><br><span>diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig</span><br><span>index 50c2802..e7b0ef7 100644</span><br><span>--- a/src/soc/intel/braswell/Kconfig</span><br><span>+++ b/src/soc/intel/braswell/Kconfig</span><br><span>@@ -40,15 +40,30 @@</span><br><span> select TSC_MONOTONIC_TIMER</span><br><span> select TSC_SYNC_MFENCE</span><br><span> select UDELAY_TSC</span><br><span style="color: hsl(0, 100%, 40%);">- select USE_GENERIC_FSP_CAR_INC</span><br><span> select INTEL_DESCRIPTOR_MODE_CAPABLE</span><br><span> select HAVE_SPI_CONSOLE_SUPPORT</span><br><span> select HAVE_FSP_GOP</span><br><span> select GENERIC_GPIO_LIB</span><br><span> select INTEL_GMA_ACPI</span><br><span> select INTEL_GMA_SWSMISCI</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOOTBLOCK_CONSOLE</span><br><span> select CPU_INTEL_COMMON</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config USE_GENERIC_FSP_CAR_INC</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default y if !C_ENVIRONMENT_BOOTBLOCK</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config DCACHE_BSP_STACK_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x2000</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ The amount of anticipated stack usage in CAR by bootblock and</span><br><span style="color: hsl(120, 100%, 40%);">+ other stages.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config C_ENV_BOOTBLOCK_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x8000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config VBOOT</span><br><span> select VBOOT_STARTS_IN_ROMSTAGE</span><br><span> </span><br><span>diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc</span><br><span>index ac1bacd..6939ddd 100644</span><br><span>--- a/src/soc/intel/braswell/Makefile.inc</span><br><span>+++ b/src/soc/intel/braswell/Makefile.inc</span><br><span>@@ -9,6 +9,8 @@</span><br><span> subdirs-y += ../../../cpu/intel/turbo</span><br><span> subdirs-y += ../../../cpu/intel/common</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += bootblock/bootblock_c.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> romstage-y += gpio_support.c</span><br><span> romstage-y += iosf.c</span><br><span> romstage-y += lpc_init.c</span><br><span>diff --git a/src/soc/intel/braswell/bootblock/bootblock_c.c b/src/soc/intel/braswell/bootblock/bootblock_c.c</span><br><span>new file mode 100644</span><br><span>index 0000000..8cb6fa8</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/braswell/bootblock/bootblock_c.c</span><br><span>@@ -0,0 +1,34 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Eltan B.V.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <bootblock_common.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <fsp/bootblock.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+asmlinkage void bootblock_c_entry(uint64_t base_timestamp)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Call lib/bootblock.c main */</span><br><span style="color: hsl(120, 100%, 40%);">+ bootblock_main_with_timestamp(base_timestamp, NULL, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_soc_early_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_soc_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "FSP TempRamInit successful\n");</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/braswell/include/soc/bootblock.h b/src/soc/intel/braswell/include/soc/bootblock.h</span><br><span>new file mode 100644</span><br><span>index 0000000..072e55d</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/braswell/include/soc/bootblock.h</span><br><span>@@ -0,0 +1,19 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Eltan B.V.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _SOC_BOOTBLOCK_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _SOC_BOOTBLOCK_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* _SOC_BOOTBLOCK_H_ */</span><br><span>diff --git a/src/soc/intel/braswell/romstage/Makefile.inc b/src/soc/intel/braswell/romstage/Makefile.inc</span><br><span>index c3ed415..7afb0b5 100644</span><br><span>--- a/src/soc/intel/braswell/romstage/Makefile.inc</span><br><span>+++ b/src/soc/intel/braswell/romstage/Makefile.inc</span><br><span>@@ -1,3 +1,4 @@</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += car_stage.S</span><br><span> romstage-y += early_spi.c</span><br><span> romstage-y += pmc.c</span><br><span> romstage-y += romstage.c</span><br><span>diff --git a/src/soc/intel/braswell/romstage/car_stage.S b/src/soc/intel/braswell/romstage/car_stage.S</span><br><span>new file mode 100644</span><br><span>index 0000000..db9f404</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/braswell/romstage/car_stage.S</span><br><span>@@ -0,0 +1,40 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2015 Google Inc</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Eltan B.V.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* I/O delay between post codes on failure */</span><br><span style="color: hsl(120, 100%, 40%);">+#define LHLT_DELAY 0x50000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+.text</span><br><span style="color: hsl(120, 100%, 40%);">+.global car_stage_entry</span><br><span style="color: hsl(120, 100%, 40%);">+car_stage_entry:</span><br><span style="color: hsl(120, 100%, 40%);">+ call romstage_c_entry</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "src/drivers/intel/fsp1_1/after_raminit.S"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ movb $0x69, %ah</span><br><span style="color: hsl(120, 100%, 40%);">+ jmp .Lhlt</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+.Lhlt:</span><br><span style="color: hsl(120, 100%, 40%);">+ xchg %al, %ah</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_POST_IO)</span><br><span style="color: hsl(120, 100%, 40%);">+ outb %al, $CONFIG_POST_IO_PORT</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(POST_DEAD_CODE)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $LHLT_DELAY, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+.Lhlt_Delay:</span><br><span style="color: hsl(120, 100%, 40%);">+ outb %al, $0xED</span><br><span style="color: hsl(120, 100%, 40%);">+ loop .Lhlt_Delay</span><br><span style="color: hsl(120, 100%, 40%);">+ jmp .Lhlt</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29662">change 29662</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29662"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c </div>
<div style="display:none"> Gerrit-Change-Number: 29662 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Frans Hendriks <fhendriks@eltan.com> </div>