<p>Mario Scheithauer has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29635">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">siemens/mc_apl5: Add new mainboard variant mc_apl5<br><br>This mainboard is based on mc_apl1. In a first step, it concerns a copy<br>of mc_apl1 directory with minimum changes. Special adaptations for<br>mc_apl5 mainboard will follow in separate commits.<br><br>Change-Id: Icdbb116a822ffa7a3bfb7026a5d1164db56a0c46<br>Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com><br>---<br>M src/mainboard/siemens/mc_apl1/Kconfig<br>M src/mainboard/siemens/mc_apl1/Kconfig.name<br>A src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig<br>A src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc<br>A src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb<br>A src/mainboard/siemens/mc_apl1/variants/mc_apl5/include/variant/ptn3460.h<br>A src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c<br>A src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c<br>8 files changed, 521 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/29635/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/siemens/mc_apl1/Kconfig b/src/mainboard/siemens/mc_apl1/Kconfig</span><br><span>index eeb5d9b..638b839 100644</span><br><span>--- a/src/mainboard/siemens/mc_apl1/Kconfig</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/Kconfig</span><br><span>@@ -20,6 +20,7 @@</span><br><span> default "mc_apl2" if BOARD_SIEMENS_MC_APL2</span><br><span> default "mc_apl3" if BOARD_SIEMENS_MC_APL3</span><br><span> default "mc_apl4" if BOARD_SIEMENS_MC_APL4</span><br><span style="color: hsl(120, 100%, 40%);">+ default "mc_apl5" if BOARD_SIEMENS_MC_APL5</span><br><span> </span><br><span> config MAINBOARD_PART_NUMBER</span><br><span> string</span><br><span>@@ -27,6 +28,7 @@</span><br><span> default "MC APL2" if BOARD_SIEMENS_MC_APL2</span><br><span> default "MC APL3" if BOARD_SIEMENS_MC_APL3</span><br><span> default "MC APL4" if BOARD_SIEMENS_MC_APL4</span><br><span style="color: hsl(120, 100%, 40%);">+ default "MC APL5" if BOARD_SIEMENS_MC_APL5</span><br><span> </span><br><span> config MAX_CPUS</span><br><span> int</span><br><span>diff --git a/src/mainboard/siemens/mc_apl1/Kconfig.name b/src/mainboard/siemens/mc_apl1/Kconfig.name</span><br><span>index 592d8aa..3a5b6a3 100644</span><br><span>--- a/src/mainboard/siemens/mc_apl1/Kconfig.name</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/Kconfig.name</span><br><span>@@ -10,6 +10,10 @@</span><br><span> bool "-> MC APL3"</span><br><span> select BOARD_SIEMENS_BASEBOARD_MC_APL1</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_SIEMENS_MC_APL5</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "-> MC APL5"</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_SIEMENS_BASEBOARD_MC_APL1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config BOARD_SIEMENS_MC_APL4</span><br><span> bool "-> MC APL4"</span><br><span> select BOARD_SIEMENS_BASEBOARD_MC_APL1</span><br><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..fd472f7</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig</span><br><span>@@ -0,0 +1,16 @@</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_SIEMENS_MC_APL5</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_SIEMENS_MC_APL5_VAR</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool y</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVER_INTEL_I210</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_I2C_RX6110SA</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVER_SIEMENS_NC_FPGA</span><br><span style="color: hsl(120, 100%, 40%);">+ select NC_FPGA_NOTIFY_CB_READY</span><br><span style="color: hsl(120, 100%, 40%);">+ select APL_SKIP_SET_POWER_LIMITS</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config DEVICETREE</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "variants/mc_apl5/devicetree.cb"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endif # BOARD_SIEMENS_MC_APL5</span><br><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..adf9aff</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc</span><br><span>@@ -0,0 +1,2 @@</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += mainboard.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += ptn3460.c</span><br><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..f3e8a77</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb</span><br><span>@@ -0,0 +1,119 @@</span><br><span style="color: hsl(120, 100%, 40%);">+chip soc/intel/apollolake</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sci_irq" = "SCIS_IRQ10"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Disable unused clkreq of PCIe root ports</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_rp_clkreq_pin[0]" = "3" # PCIe-PCI-Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_rp_clkreq_pin[1]" = "2" # FPGA</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_rp_clkreq_pin[2]" = "0" # MACPHY</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_rp_clkreq_pin[3]" = "1" # MACPHY</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # EMMC TX DATA Delay 1</span><br><span style="color: hsl(120, 100%, 40%);">+ # Refer to EDS-Vol2-22.3.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [14:8] steps of delay for HS400, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [6:0] steps of delay for SDR104/HS200, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "emmc_tx_data_cntl1" = "0x0C16"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # EMMC TX DATA Delay 2</span><br><span style="color: hsl(120, 100%, 40%);">+ # Refer to EDS-Vol2-22.3.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [30:24] steps of delay for SDR50, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [22:16] steps of delay for DDR50, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [14:8] steps of delay for SDR25/HS50, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [6:0] steps of delay for SDR12, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "emmc_tx_data_cntl2" = "0x28162828"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # EMMC RX CMD/DATA Delay 1</span><br><span style="color: hsl(120, 100%, 40%);">+ # Refer to EDS-Vol2-22.3.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [30:24] steps of delay for SDR50, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [22:16] steps of delay for DDR50, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [14:8] steps of delay for SDR25/HS50, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [6:0] steps of delay for SDR12, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "emmc_rx_cmd_data_cntl1" = "0x00181717"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # EMMC RX CMD/DATA Delay 2</span><br><span style="color: hsl(120, 100%, 40%);">+ # Refer to EDS-Vol2-22.3.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [17:16] stands for Rx Clock before Output Buffer</span><br><span style="color: hsl(120, 100%, 40%);">+ # [14:8] steps of delay for Auto Tuning Mode, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [6:0] steps of delay for HS200, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "emmc_rx_cmd_data_cntl2" = "0x10008"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # 0:HS400(Default), 1:HS200, 2:DDR50</span><br><span style="color: hsl(120, 100%, 40%);">+ register "emmc_host_max_speed" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Intel Common SoC Config</span><br><span style="color: hsl(120, 100%, 40%);">+ #+-------------------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Field | Value |</span><br><span style="color: hsl(120, 100%, 40%);">+ #+-------------------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ #| I2C0 | Proximity Sensor |</span><br><span style="color: hsl(120, 100%, 40%);">+ #+-------------------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "common_soc_config" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .i2c[0] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed = I2C_SPEED_STANDARD</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end # - Host Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.1 off end # - DPTF</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.2 off end # - NPK</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 on end # - Gen - Display</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 03.0 off end # - Iunit</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0d.0 on end # - P2SB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0d.1 off end # - PMC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0d.2 on end # - SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0d.3 off end # - Shared SRAM</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0e.0 off end # - Audio</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 11.0 on end # - ISH</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.0 on end # - SATA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 13.0 on end # - RP 2 - PCIe A 0 - MACPHY</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 13.1 on end # - RP 3 - PCIe A 1 - MACPHY</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 13.2 off end # - RP 4 - PCIe-A 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 13.3 off end # - RP 5 - PCIe-A 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on end # - RP 0 - PCIe-B 0 - PCIe-PCI-Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.1 on end # - RP 1 - PCIe-B 1 - FPGA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.0 on end # - XHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.1 off end # - XDCI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 on # - I2C 0</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable external RTC chip</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/i2c/rx6110sa</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pmon_sampling" = "PMON_SAMPL_256_MS"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "bks_on" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "bks_off" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "iocut_en" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "set_user_date" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "user_year" = "04"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "user_month" = "07"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "user_day" = "01"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "user_weekday" = "4"</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 0x32 on end # RTC RX6110 SA</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.1 off end # - I2C 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.2 off end # - I2C 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.3 off end # - I2C 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.0 off end # - I2C 4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.1 off end # - I2C 5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.2 off end # - I2C 6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.3 on end # - I2C 7</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.0 on end # - UART 0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.1 on end # - UART 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.2 on end # - UART 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.3 on end # - UART 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.0 off end # - SPI 0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.1 off end # - SPI 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.2 off end # - SPI 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.0 off end # - PWM</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1b.0 off end # - SDCARD</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on end # - eMMC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 off end # - UFS</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 off end # - SDIO</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on end # - LPC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.1 on end # - SMBUS</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/include/variant/ptn3460.h b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/include/variant/ptn3460.h</span><br><span>new file mode 100644</span><br><span>index 0000000..6ae3e2f</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/include/variant/ptn3460.h</span><br><span>@@ -0,0 +1,91 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014-2017 Siemens AG</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef PTN3460_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define PTN3460_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PTN_SLAVE_ADR 0x20</span><br><span style="color: hsl(120, 100%, 40%);">+#define PTN_I2C_CONTROLLER 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PTN_EDID_OFF 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+#define PTN_EDID_LEN 0x80</span><br><span style="color: hsl(120, 100%, 40%);">+#define PTN_CONFIG_OFF 0x80</span><br><span style="color: hsl(120, 100%, 40%);">+#define PTN_FLASH_CFG_OFF 0xE8</span><br><span style="color: hsl(120, 100%, 40%);">+#define PTN_FLASH_CFG_LEN 0x04</span><br><span style="color: hsl(120, 100%, 40%);">+#define PTN_MAX_EDID_NUM 6</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Define some error codes that can be used. */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PTN_NO_ERROR 0x00000000</span><br><span style="color: hsl(120, 100%, 40%);">+#define PTN_BUS_ERROR 0x10000000</span><br><span style="color: hsl(120, 100%, 40%);">+#define PTN_INVALID_EDID 0x20000000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct ptn_3460_config {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DiplayPort interface control. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t dp_interface_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* LVDS interface control register 1. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t lvds_interface_ctrl1;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* LVDS interface control register 2. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t lvds_interface_ctrl2;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* LVDS interface control register 3. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t lvds_interface_ctrl3;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Select which EDID-block is emulated. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t edid_rom_emulation;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Select which EDID block to map to 0..0x7F. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t edid_rom_access_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Smallest PWM frequency for back light. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t pwm_min[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Biggest PWM frequency for back light. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t pwm_max[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Fast link training control register. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t fast_link_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin configuration control register 1. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t pin_cfg_ctrl1;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin configuration control register 2. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t pin_cfg_ctrl2;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Default PWM bit count in DPCD register. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t pwm_default;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Current PWM bit count in DPCD register. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t pwm_value;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Default PWM frequency in DPCD register. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t pwm_default_freq;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Panel T3 timing value. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t t3_timing;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Panel T12 timing value. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t t12_timing;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Back light control register. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t backlight_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Panel T2 delay. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t t2_delay;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Panel T4 timing value. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t t4_timing;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Panel T5 delay. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t t5_delay;</span><br><span style="color: hsl(120, 100%, 40%);">+} __packed;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct ptn_3460_flash {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Flash command (erase or erase and flash). */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t cmd;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Magic number needed by the flash algorithm. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t magic;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Trigger for starting flash operation. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t trigger;</span><br><span style="color: hsl(120, 100%, 40%);">+} __packed;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int ptn3460_init(const char *hwi_block);</span><br><span style="color: hsl(120, 100%, 40%);">+int ptn3460_write_edid(uint8_t edid_num, const uint8_t data[PTN_EDID_LEN]);</span><br><span style="color: hsl(120, 100%, 40%);">+int ptn_select_edid(uint8_t edid_num);</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* PTN3460_H_ */</span><br><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c</span><br><span>new file mode 100644</span><br><span>index 0000000..6d22fd9</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c</span><br><span>@@ -0,0 +1,110 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Siemens AG</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <bootstate.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_ops.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <hwilib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/lpc_lib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/pcr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pcr_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <timer.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <timestamp.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variants.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <variant/ptn3460.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define TX_DWORD3 0xa8c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void variant_mainboard_final(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int status;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set up the DP2LVDS converter.</span><br><span style="color: hsl(120, 100%, 40%);">+ * ptn3460_init() may only be executed after i2c bus init.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ status = ptn3460_init("hwinfo.hex");</span><br><span style="color: hsl(120, 100%, 40%);">+ if (status)</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "LCD: Set up PTN with status 0x%x\n", status);</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "LCD: Set up PTN was successful.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * PIR6 register mapping for PCIe root ports</span><br><span style="color: hsl(120, 100%, 40%);">+ * INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA#</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write16(PID_ITSS, 0x314c, 0x0321);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */</span><br><span style="color: hsl(120, 100%, 40%);">+ dev = dev_find_device(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2001, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev)</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(dev, 0xd8, 0x3e);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable CLKRUN_EN for power gating LPC */</span><br><span style="color: hsl(120, 100%, 40%);">+ lpc_enable_pci_clk_cntl();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enable LPC PCE (Power Control Enable) by setting IOSF-SB port 0xD2</span><br><span style="color: hsl(120, 100%, 40%);">+ * offset 0x341D bit3 and bit0.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enable LPC CCE (Clock Control Enable) by setting IOSF-SB port 0xD2</span><br><span style="color: hsl(120, 100%, 40%);">+ * offset 0x341C bit [3:0].</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Correct the SATA transmit signal via the High Speed I/O Transmit</span><br><span style="color: hsl(120, 100%, 40%);">+ * Control Register 3.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Bit [23:16] set the output voltage swing for TX line.</span><br><span style="color: hsl(120, 100%, 40%);">+ * The value 0x4a sets the swing level to 0.58 V.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_rmw32(PID_MODPHY, TX_DWORD3, (0x00 << 16), (0x4a << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void wait_for_legacy_dev(void *unused)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t legacy_delay, us_since_boot;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct stopwatch sw;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Open main hwinfo block. */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS)</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Get legacy delay parameter from hwinfo. */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (hwilib_get_field(LegacyDelay, (uint8_t *) &legacy_delay,</span><br><span style="color: hsl(120, 100%, 40%);">+ sizeof(legacy_delay)) != sizeof(legacy_delay))</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ us_since_boot = get_us_since_boot();</span><br><span style="color: hsl(120, 100%, 40%);">+ /* No need to wait if the time since boot is already long enough.*/</span><br><span style="color: hsl(120, 100%, 40%);">+ if (us_since_boot > legacy_delay)</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+ stopwatch_init_msecs_expire(&sw, (legacy_delay - us_since_boot) / 1000);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_NOTICE, "Wait remaining %d of %d us for legacy devices...",</span><br><span style="color: hsl(120, 100%, 40%);">+ legacy_delay - us_since_boot, legacy_delay);</span><br><span style="color: hsl(120, 100%, 40%);">+ stopwatch_wait_until_expired(&sw);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_NOTICE, "done!\n");</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void finalize_boot(void *unused)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set coreboot ready LED. */</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_output(CNV_RGI_DT, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, wait_for_legacy_dev, NULL);</span><br><span style="color: hsl(120, 100%, 40%);">+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL);</span><br><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c</span><br><span>new file mode 100644</span><br><span>index 0000000..829af2a</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c</span><br><span>@@ -0,0 +1,177 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014-2017 Siemens AG</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <lib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <hwilib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/i2c_simple.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <variant/ptn3460.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * This function sets up the DP2LVDS-converter to be used with the appropriate</span><br><span style="color: hsl(120, 100%, 40%);">+ * lcd panel.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * @param *hwi_block Filename in CBFS of the block to use as HW-Info.</span><br><span style="color: hsl(120, 100%, 40%);">+ * @return 0 on success or HWI-Data/PTN error code.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+int ptn3460_init(const char *hwi_block)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct ptn_3460_config cfg;</span><br><span style="color: hsl(120, 100%, 40%);">+ int status;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t disp_con = 0, color_depth = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t edid_data[PTN_EDID_LEN];</span><br><span style="color: hsl(120, 100%, 40%);">+ int i;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!hwi_block || hwilib_find_blocks(hwi_block) != CB_SUCCESS) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ hwi_block);</span><br><span style="color: hsl(120, 100%, 40%);">+ return 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Get all needed information from hwinfo block. */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (hwilib_get_field(Edid, edid_data, sizeof(edid_data)) !=</span><br><span style="color: hsl(120, 100%, 40%);">+ sizeof(edid_data)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "LCD: No EDID data available in %s\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ hwi_block);</span><br><span style="color: hsl(120, 100%, 40%);">+ return 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((hwilib_get_field(PF_DisplCon, &disp_con, sizeof(disp_con)) !=</span><br><span style="color: hsl(120, 100%, 40%);">+ sizeof(disp_con))) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "LCD: Missing panel features from %s\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ hwi_block);</span><br><span style="color: hsl(120, 100%, 40%);">+ return 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ if (hwilib_get_field(PF_Color_Depth, &color_depth, sizeof(color_depth))</span><br><span style="color: hsl(120, 100%, 40%);">+ != sizeof(color_depth)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "LCD: Missing panel features from %s\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ hwi_block);</span><br><span style="color: hsl(120, 100%, 40%);">+ return 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Here, all the desired information for setting up DP2LVDS converter</span><br><span style="color: hsl(120, 100%, 40%);">+ * is present. Inside the converter, table 6 will be used for the</span><br><span style="color: hsl(120, 100%, 40%);">+ * timings.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ status = ptn3460_write_edid(6, edid_data);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (status)</span><br><span style="color: hsl(120, 100%, 40%);">+ return status;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Select this table to be emulated. */</span><br><span style="color: hsl(120, 100%, 40%);">+ ptn_select_edid(6);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Read PTN configuration data. */</span><br><span style="color: hsl(120, 100%, 40%);">+ status = i2c_read_bytes(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR,</span><br><span style="color: hsl(120, 100%, 40%);">+ PTN_CONFIG_OFF, (uint8_t *)&cfg,</span><br><span style="color: hsl(120, 100%, 40%);">+ sizeof(cfg));</span><br><span style="color: hsl(120, 100%, 40%);">+ if (status)</span><br><span style="color: hsl(120, 100%, 40%);">+ return (PTN_BUS_ERROR | status);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set up configuration data according to the hwinfo block we get. */</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg.dp_interface_ctrl = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg.lvds_interface_ctrl1 = 0x00;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (disp_con == PF_DISPLCON_LVDS_DUAL)</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Turn on dual LVDS lane and clock. */</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg.lvds_interface_ctrl1 |= 0x0b;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (color_depth == PF_COLOR_DEPTH_6BIT)</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Use 18 bits per pixel. */</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg.lvds_interface_ctrl1 |= 0x20;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 1 % clock spreading, 300 mV LVDS swing. */</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg.lvds_interface_ctrl2 = 0x13;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* No LVDS signal swap. */</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg.lvds_interface_ctrl3 = 0x00;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Delay T2 (VDD to LVDS active) by 16 ms. */</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg.t2_delay = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 250 ms from LVDS to backlight active. */</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg.t3_timing = 10;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 1 second re-power delay. */</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg.t12_timing = 20;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 150 ms backlight off to LVDS inactive. */</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg.t4_timing = 3;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Delay T5 (LVDS to VDD inactive) by 16 ms. */</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg.t5_delay = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable backlight control. */</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg.backlight_ctrl = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Write back configuration data to PTN3460. */</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < sizeof(struct ptn_3460_config); i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR,</span><br><span style="color: hsl(120, 100%, 40%);">+ PTN_CONFIG_OFF+i,</span><br><span style="color: hsl(120, 100%, 40%);">+ *(((uint8_t *)&cfg)+i));</span><br><span style="color: hsl(120, 100%, 40%);">+ if (status)</span><br><span style="color: hsl(120, 100%, 40%);">+ return (PTN_BUS_ERROR | status);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Read PTN configuration data. */</span><br><span style="color: hsl(120, 100%, 40%);">+ status = i2c_read_bytes(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR,</span><br><span style="color: hsl(120, 100%, 40%);">+ PTN_CONFIG_OFF, (uint8_t *)&cfg, sizeof(cfg));</span><br><span style="color: hsl(120, 100%, 40%);">+ if (status)</span><br><span style="color: hsl(120, 100%, 40%);">+ return (PTN_BUS_ERROR | status);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return PTN_NO_ERROR;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * This function writes one Extended Display Identification Data (EDID)</span><br><span style="color: hsl(120, 100%, 40%);">+ * structure to PTN3460.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * @param edid_num Number of EDID that must be written (0..6).</span><br><span style="color: hsl(120, 100%, 40%);">+ * @param *data Pointer to a buffer where data to write is stored in.</span><br><span style="color: hsl(120, 100%, 40%);">+ * @return 0 on success or error code.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+int ptn3460_write_edid(uint8_t edid_num, const uint8_t data[PTN_EDID_LEN])</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int status;</span><br><span style="color: hsl(120, 100%, 40%);">+ int i;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (edid_num > PTN_MAX_EDID_NUM)</span><br><span style="color: hsl(120, 100%, 40%);">+ return PTN_INVALID_EDID;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* First enable access to the desired EDID table. */</span><br><span style="color: hsl(120, 100%, 40%);">+ status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR,</span><br><span style="color: hsl(120, 100%, 40%);">+ PTN_CONFIG_OFF + 5, edid_num);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (status)</span><br><span style="color: hsl(120, 100%, 40%);">+ return (PTN_BUS_ERROR | status);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Now we can simply write EDID-data to ptn3460. */</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < PTN_EDID_LEN; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR,</span><br><span style="color: hsl(120, 100%, 40%);">+ PTN_EDID_OFF + i, data[i]);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (status)</span><br><span style="color: hsl(120, 100%, 40%);">+ return (PTN_BUS_ERROR | status);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return PTN_NO_ERROR;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * This function selects one of 7 EDID-tables inside PTN3460 which should be</span><br><span style="color: hsl(120, 100%, 40%);">+ * emulated on DisplayPort and turn emulation ON.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * @param edid_num Number of EDID to emulate (0..6).</span><br><span style="color: hsl(120, 100%, 40%);">+ * @return 0 on success or error code.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+int ptn_select_edid(uint8_t edid_num)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int status;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t val;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (edid_num > PTN_MAX_EDID_NUM)</span><br><span style="color: hsl(120, 100%, 40%);">+ return PTN_INVALID_EDID;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable emulation of the desired EDID table. */</span><br><span style="color: hsl(120, 100%, 40%);">+ val = (edid_num << 1) | 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR,</span><br><span style="color: hsl(120, 100%, 40%);">+ PTN_CONFIG_OFF + 4, val);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (status)</span><br><span style="color: hsl(120, 100%, 40%);">+ return (PTN_BUS_ERROR | status);</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ return PTN_NO_ERROR;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29635">change 29635</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Icdbb116a822ffa7a3bfb7026a5d1164db56a0c46 </div>
<div style="display:none"> Gerrit-Change-Number: 29635 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Mario Scheithauer <mario.scheithauer@siemens.com> </div>