<p>Mario Scheithauer has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29632">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">siemens/mc_apl4: Clean up ramstage<br><br>Currently, there is nothing for this mainboard to do in ramstage.<br><br>Change-Id: Id74a5f3f0a0583dc6bc81044913b8bb83d3b0b93<br>Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com><br>---<br>M src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig<br>M src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc<br>D src/mainboard/siemens/mc_apl1/variants/mc_apl4/mainboard.c<br>3 files changed, 0 insertions(+), 104 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/29632/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig</span><br><span>index 3cf7406..ea81c6c 100644</span><br><span>--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig</span><br><span>@@ -4,10 +4,6 @@</span><br><span> config BOARD_SIEMENS_MC_APL4_VAR</span><br><span> def_bool y</span><br><span> select DRIVER_INTEL_I210</span><br><span style="color: hsl(0, 100%, 40%);">- select DRIVERS_I2C_RX6110SA</span><br><span style="color: hsl(0, 100%, 40%);">- select DRIVER_SIEMENS_NC_FPGA</span><br><span style="color: hsl(0, 100%, 40%);">- select NC_FPGA_NOTIFY_CB_READY</span><br><span style="color: hsl(0, 100%, 40%);">- select APL_SKIP_SET_POWER_LIMITS</span><br><span> </span><br><span> config DEVICETREE</span><br><span> string</span><br><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc</span><br><span>index caf542f..fd45b94 100644</span><br><span>--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc</span><br><span>@@ -1,3 +1 @@</span><br><span> romstage-y += memory.c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += mainboard.c</span><br><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/mainboard.c</span><br><span>deleted file mode 100644</span><br><span>index ccf3ab8..0000000</span><br><span>--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/mainboard.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,98 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2018 Siemens AG</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <bootstate.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ops.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <hwilib.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/lpc_lib.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/pcr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/pcr_ids.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <timer.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <timestamp.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <baseboard/variants.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define TX_DWORD3 0xa8c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void variant_mainboard_final(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- struct device *dev = NULL;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * PIR6 register mapping for PCIe root ports</span><br><span style="color: hsl(0, 100%, 40%);">- * INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA#</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- pcr_write16(PID_ITSS, 0x314c, 0x0321);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */</span><br><span style="color: hsl(0, 100%, 40%);">- dev = dev_find_device(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2001, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- if (dev)</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(dev, 0xd8, 0x3e);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable CLKRUN_EN for power gating LPC */</span><br><span style="color: hsl(0, 100%, 40%);">- lpc_enable_pci_clk_cntl();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Enable LPC PCE (Power Control Enable) by setting IOSF-SB port 0xD2</span><br><span style="color: hsl(0, 100%, 40%);">- * offset 0x341D bit3 and bit0.</span><br><span style="color: hsl(0, 100%, 40%);">- * Enable LPC CCE (Clock Control Enable) by setting IOSF-SB port 0xD2</span><br><span style="color: hsl(0, 100%, 40%);">- * offset 0x341C bit [3:0].</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Correct the SATA transmit signal via the High Speed I/O Transmit</span><br><span style="color: hsl(0, 100%, 40%);">- * Control Register 3.</span><br><span style="color: hsl(0, 100%, 40%);">- * Bit [23:16] set the output voltage swing for TX line.</span><br><span style="color: hsl(0, 100%, 40%);">- * The value 0x4a sets the swing level to 0.58 V.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- pcr_rmw32(PID_MODPHY, TX_DWORD3, (0x00 << 16), (0x4a << 16));</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void wait_for_legacy_dev(void *unused)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t legacy_delay, us_since_boot;</span><br><span style="color: hsl(0, 100%, 40%);">- struct stopwatch sw;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Open main hwinfo block. */</span><br><span style="color: hsl(0, 100%, 40%);">- if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS)</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Get legacy delay parameter from hwinfo. */</span><br><span style="color: hsl(0, 100%, 40%);">- if (hwilib_get_field(LegacyDelay, (uint8_t *) &legacy_delay,</span><br><span style="color: hsl(0, 100%, 40%);">- sizeof(legacy_delay)) != sizeof(legacy_delay))</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- us_since_boot = get_us_since_boot();</span><br><span style="color: hsl(0, 100%, 40%);">- /* No need to wait if the time since boot is already long enough.*/</span><br><span style="color: hsl(0, 100%, 40%);">- if (us_since_boot > legacy_delay)</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">- stopwatch_init_msecs_expire(&sw, (legacy_delay - us_since_boot) / 1000);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_NOTICE, "Wait remaining %d of %d us for legacy devices...",</span><br><span style="color: hsl(0, 100%, 40%);">- legacy_delay - us_since_boot, legacy_delay);</span><br><span style="color: hsl(0, 100%, 40%);">- stopwatch_wait_until_expired(&sw);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_NOTICE, "done!\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void finalize_boot(void *unused)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set coreboot ready LED. */</span><br><span style="color: hsl(0, 100%, 40%);">- gpio_output(CNV_RGI_DT, 1);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, wait_for_legacy_dev, NULL);</span><br><span style="color: hsl(0, 100%, 40%);">-BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL);</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29632">change 29632</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29632"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id74a5f3f0a0583dc6bc81044913b8bb83d3b0b93 </div>
<div style="display:none"> Gerrit-Change-Number: 29632 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Mario Scheithauer <mario.scheithauer@siemens.com> </div>