<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29629">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/{intel/google}: Make static IRQ mapping for PIC mode<br><br>This patch makes static PIRQ->IRQ mapping, where IRQ10 is mapped<br>to PBRC and IRQ11 is mapped for PARC/PCRC/PDRC/PERC/PFRC/PGRC/PHRC.<br><br>Change-Id: I8722e34841fe53a4d425202b915ac7838af0d859<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/mainboard/google/sarien/variants/arcada/devicetree.cb<br>M src/mainboard/google/sarien/variants/sarien/devicetree.cb<br>M src/mainboard/google/zoombini/variants/baseboard/devicetree.cb<br>M src/mainboard/google/zoombini/variants/meowth/devicetree.cb<br>M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb<br>M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb<br>M src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb<br>M src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb<br>M src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb<br>9 files changed, 81 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/29629/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb</span><br><span>index ee1cca0..29c644a 100644</span><br><span>--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb</span><br><span>+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb</span><br><span>@@ -28,6 +28,15 @@</span><br><span>      register "SkipExtGfxScan" = "1"</span><br><span>  register "VmxEnable" = "1"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqa_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqb_routing" = "PCH_IRQ10"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqc_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqd_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqe_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqf_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqg_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqh_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>         register "speed_shift_enable" = "1"</span><br><span>      register "s0ix_enable" = "1"</span><br><span> </span><br><span>diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb</span><br><span>index b33c923..13143f1 100644</span><br><span>--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb</span><br><span>+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb</span><br><span>@@ -28,6 +28,15 @@</span><br><span>   register "SkipExtGfxScan" = "1"</span><br><span>  register "VmxEnable" = "1"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqa_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqb_routing" = "PCH_IRQ10"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqc_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqd_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqe_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqf_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqg_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqh_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>         register "speed_shift_enable" = "1"</span><br><span>      register "s0ix_enable" = "1"</span><br><span> </span><br><span>diff --git a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb</span><br><span>index c7ef264..592f2aa 100644</span><br><span>--- a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb</span><br><span>+++ b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb</span><br><span>@@ -18,6 +18,15 @@</span><br><span>               device lapic 0 on end</span><br><span>        end</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+       register "pirqa_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqb_routing" = "PCH_IRQ10"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqc_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqd_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqe_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqf_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqg_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqh_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>         # FSP configuration</span><br><span>  register "SaGv" = "3"</span><br><span>    register "SmbusEnable" = "1"</span><br><span>diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb</span><br><span>index c3a546e..af7c01b 100644</span><br><span>--- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb</span><br><span>+++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb</span><br><span>@@ -27,6 +27,15 @@</span><br><span>               device lapic 0 on end</span><br><span>        end</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+       register "pirqa_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqb_routing" = "PCH_IRQ10"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqc_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqd_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqe_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqf_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqg_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqh_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>         # FSP configuration</span><br><span>  register "SaGv" = "SaGv_Enabled"</span><br><span>         register "SmbusEnable" = "1"</span><br><span>diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb</span><br><span>index da439d5..d255b16 100644</span><br><span>--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb</span><br><span>@@ -30,6 +30,15 @@</span><br><span>       register "PchHdaDspEnable" = "1"</span><br><span>         register "PchHdaAudioLinkHda" = "1"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+   register "pirqa_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqb_routing" = "PCH_IRQ10"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqc_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqd_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqe_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqf_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqg_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqh_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>         register "PcieRpEnable[0]" = "1"</span><br><span>         register "PcieRpEnable[1]" = "1"</span><br><span>         register "PcieRpEnable[2]" = "1"</span><br><span>diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb</span><br><span>index a1c8586..40d8802 100644</span><br><span>--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb</span><br><span>@@ -32,6 +32,15 @@</span><br><span>   register "PchHdaAudioLinkSsp0" = "1"</span><br><span>     register "PchHdaAudioLinkSsp1" = "1"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+  register "pirqa_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqb_routing" = "PCH_IRQ10"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqc_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqd_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqe_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqf_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqg_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqh_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>         register "PcieRpEnable[0]" = "1"</span><br><span>         register "PcieRpEnable[1]" = "1"</span><br><span>         register "PcieRpEnable[2]" = "1"</span><br><span>diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb</span><br><span>index 2b47f00..aa04c60 100644</span><br><span>--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb</span><br><span>@@ -46,6 +46,15 @@</span><br><span>   register "SataPortsEnable[6]" = "1"</span><br><span>      register "SataPortsEnable[7]" = "1"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+   register "pirqa_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqb_routing" = "PCH_IRQ10"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqc_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqd_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqe_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqf_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqg_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqh_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>         register "PchHdaDspEnable" = "0"</span><br><span>         register "PchHdaAudioLinkHda" = "1"</span><br><span> </span><br><span>diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb</span><br><span>index da439d5..d255b16 100644</span><br><span>--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb</span><br><span>@@ -30,6 +30,15 @@</span><br><span>    register "PchHdaDspEnable" = "1"</span><br><span>         register "PchHdaAudioLinkHda" = "1"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+   register "pirqa_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqb_routing" = "PCH_IRQ10"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqc_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqd_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqe_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqf_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqg_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqh_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>         register "PcieRpEnable[0]" = "1"</span><br><span>         register "PcieRpEnable[1]" = "1"</span><br><span>         register "PcieRpEnable[2]" = "1"</span><br><span>diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb</span><br><span>index 010ad65..3ae8700 100644</span><br><span>--- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb</span><br><span>@@ -40,6 +40,15 @@</span><br><span>   register "PchHdaDspEnable" = "1"</span><br><span>         register "PchHdaAudioLinkHda" = "1"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+   register "pirqa_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqb_routing" = "PCH_IRQ10"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqc_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqd_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqe_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqf_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqg_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "pirqh_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>         register "PcieRpEnable[0]" = "1"</span><br><span>         register "PcieRpEnable[1]" = "1"</span><br><span>         register "PcieRpEnable[2]" = "1"</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29629">change 29629</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29629"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I8722e34841fe53a4d425202b915ac7838af0d859 </div>
<div style="display:none"> Gerrit-Change-Number: 29629 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>