<p>Werner Zeh <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/29560">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Werner Zeh: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">siemens/mc_apl4: Remove external RTC from I2C0<br><br>This mainboard also has an external RTC chip, but not on this bus. The<br>topic is currently in clarification and will be published with a later<br>patch. In a first step we enable all I2C busses.<br><br>Change-Id: I9ec9631ed15ab30cc6a4594531521f4a1419ad00<br>Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com><br>Reviewed-on: https://review.coreboot.org/29560<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Werner Zeh <werner.zeh@siemens.com><br>---<br>M src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb<br>1 file changed, 7 insertions(+), 21 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb</span><br><span>index 61e8c71..d03623a 100644</span><br><span>--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb</span><br><span>@@ -68,27 +68,13 @@</span><br><span> device pci 14.1 on end # - RP 1 - PCIe-B 1</span><br><span> device pci 15.0 on end # - XHCI</span><br><span> device pci 15.1 off end # - XDCI</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 16.0 on # - I2C 0</span><br><span style="color: hsl(0, 100%, 40%);">- # Enable external RTC chip</span><br><span style="color: hsl(0, 100%, 40%);">- chip drivers/i2c/rx6110sa</span><br><span style="color: hsl(0, 100%, 40%);">- register "pmon_sampling" = "PMON_SAMPL_256_MS"</span><br><span style="color: hsl(0, 100%, 40%);">- register "bks_on" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">- register "bks_off" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "iocut_en" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "set_user_date" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "user_year" = "04"</span><br><span style="color: hsl(0, 100%, 40%);">- register "user_month" = "07"</span><br><span style="color: hsl(0, 100%, 40%);">- register "user_day" = "01"</span><br><span style="color: hsl(0, 100%, 40%);">- register "user_weekday" = "4"</span><br><span style="color: hsl(0, 100%, 40%);">- device i2c 0x32 on end # RTC RX6110 SA</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 16.1 off end # - I2C 1</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 16.2 off end # - I2C 2</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 16.3 off end # - I2C 3</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 17.0 off end # - I2C 4</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 17.1 off end # - I2C 5</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 17.2 off end # - I2C 6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 on end # - I2C 0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.1 on end # - I2C 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.2 on end # - I2C 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.3 on end # - I2C 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.0 on end # - I2C 4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.1 on end # - I2C 5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.2 on end # - I2C 6</span><br><span> device pci 17.3 on end # - I2C 7</span><br><span> device pci 18.0 on end # - UART 0</span><br><span> device pci 18.1 on end # - UART 1</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29560">change 29560</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29560"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: merged </div>
<div style="display:none"> Gerrit-Change-Id: I9ec9631ed15ab30cc6a4594531521f4a1419ad00 </div>
<div style="display:none"> Gerrit-Change-Number: 29560 </div>
<div style="display:none"> Gerrit-PatchSet: 3 </div>
<div style="display:none"> Gerrit-Owner: Mario Scheithauer <mario.scheithauer@siemens.com> </div>
<div style="display:none"> Gerrit-Reviewer: Werner Zeh <werner.zeh@siemens.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>